Support TTBR1 as well as TTBR0 #19
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Disable tests when building without debug assertions.
The checks can be done in RootTable.
src/paging.rs
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| @@ -25,6 +25,17 @@ pub const PAGE_SIZE: usize = 1 << PAGE_SHIFT; | |||
| /// page size. | |||
| pub const BITS_PER_LEVEL: usize = PAGE_SHIFT - 3; | |||
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| /// Which TTBR register to use for a page table. | |||
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Maybe it's easiest to use the register names, but you could alternatively be slightly more abstract and refer to the lower or upper VA range; that's the ARM ARM terminology.
src/linearmap.rs
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| // The first page in the region covered by TTBR1. | ||
| assert_eq!( | ||
| translation.virtual_to_physical(VirtualAddress(0xffffff8000000000)), |
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Could we add underscores to make these more readable - 0xffff_ff80_0000_0000? Or compute it some other way, so it's obvious? -GIB_512, perhaps.
src/linearmap.rs
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| @@ -318,10 +373,29 @@ mod tests { | |||
| ) | |||
| } | |||
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| #[test] | |||
| fn virtual_address_range_ttbr1() { | |||
| const GIB_512: isize = 512 * 1024 * 1024 * 1024; | |||
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Extract to top level rather than repeating?
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Uh, why can't the linear map be used with |
Apologies, you're quite right - I got confused and read 'identity map' instead of 'linear map'. Ignore me ... |
src/paging.rs
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| /// will be used with `TTBR0`. | ||
| Lower, | ||
| /// The page table covers the top of the virtual address space (ending at address | ||
| /// 0xffffffffffffffff), so will be used with `TTBR1`. |
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nit: 0xffff_ffff_ffff_ffff
Fixes #14.