Add RISCV vector extension #289
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include/cpuinfo_riscv.h
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| @@ -36,6 +36,7 @@ typedef struct { | |||
| int D : 1; // Standard Extension for Double-Precision Floating-Point | |||
| int Q : 1; // Standard Extension for Quad-Precision Floating-Point | |||
| int C : 1; // Standard Extension for Compressed Instructions | |||
| int V : 1; // Standard Extneions for Vector Instructions | |||
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Ok, I've fixed the typo in the comment. |
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@michael-roe I originally implemented only the ratified extensions from the spec, that's why vector extension is missing. Do you know of any board that currently supports vector extensions? |
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Yes, I can add a test case. (I was kind of expecting you to ask for one...) The QEMU emulator can emulate V, and there are implementations on FPGA. As far as I know, current boards don't support it (Allwinner D1 is based on an obsolete version of the vector spec), but things are moving fairly quickly. |
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Last kernel news about it AFAIK proposal in September 2021 November 2022 |
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Ok, I've added tests for the V extension. |
test/cpuinfo_riscv_test.cc
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| ResetHwcaps(); | ||
| auto& fs = GetEmptyFilesystem(); | ||
| fs.CreateFile("/proc/cpuinfo", R"( |
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could you format these lines?
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Ok, I've fixed the indentation.
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Is this PR Ok now? (There are a bunch of people who want rto use riscv vector) |
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Sorry for the lag and thx for the PR! |
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please notice https://elixir.bootlin.com/linux/latest/source/arch/riscv/include/asm/hwcap.h still does not contain it so we could change this implementation if the kernel want to go in a different way... |
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