Fixes ReRAM Verilog-A model naming convention.

Signed-off-by: Ethan Mahintorabi <ethanmoon@google.com>
google · Nov 25, 2021 · 48c8310 · 48c8310
2 parents d3c4505 + 31cefa6
commit 48c8310
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/cells/reram_cell/sky130_fd_pr_reram__reram_cell.va b/cells/reram_cell/sky130_fd_pr_reram__reram_cell.va
@@ -17,7 +17,7 @@
 `include "constants.vams"
 `include "disciplines.vams"
 
-module rram2(TE, BE);
+module sky130_fd_pr_reram__reram_cell(TE, BE);
     inout TE; // top electrode
     inout BE; // bottom electrode
     electrical TE, BE;