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Missing attributes in LEF files (.magic.lef) for VNB and VPB pins #172

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agorararmard opened this issue Oct 8, 2020 · 10 comments · Fixed by #196
Closed

Missing attributes in LEF files (.magic.lef) for VNB and VPB pins #172

agorararmard opened this issue Oct 8, 2020 · 10 comments · Fixed by #196
Labels
files-layout-lef-magic Issues related to the Library Exchange Format (LEF) files generated by Magic. lib-sky130_fd_sc_hd Issues with the "high density" digital standard cells provided by the SkyWater foundry. lib-sky130_fd_sc_hdll Issues with the "high density low leakage" digital standard cells provided by the SkyWater foundry. lib-sky130_fd_sc_hs Issues with the "high speed" digital standard cells provided by the SkyWater foundry. lib-sky130_fd_sc_hvl Issues with the "high voltage" digital standard cells provided by the SkyWater foundry. lib-sky130_fd_sc_lp Issues with the "low power" digital standard cells provided by the SkyWater foundry. lib-sky130_fd_sc_ls Issues with the "low speed" digital standard cells provided by the SkyWater foundry. lib-sky130_fd_sc_ms Issues with the "medium speed" digital standard cells provided by the SkyWater foundry. type-bug Something isn't working

Comments

@agorararmard
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Expected Behavior

The USE and DIRECTION sections should be added because this is causing parsing errors and warnings with some of the opensource tools, i.e.: OpenROAD and OpenPhySyn.

PIN VPB
    USE POWER ;
    DIRECTION INOUT ;
    PORT
      LAYER nwell ;
        RECT -0.190000 1.305000 2.950000 2.910000 ;
    END
  END VPB

For VNB it should be: USE GROUND ;

I'm not sure if the DIRECTION is a must tho, but it would be nice to have. Also, I'm not sure if SHAPE ABUTMENT ; should be added as well.

Actual Behavior

In all cells of all libraries, VNB and VPB pins are missing the USE and DIRECTION sections.
i.e.:

PIN VPB
    PORT
      LAYER nwell ;
        RECT -0.190000 1.305000 2.950000 2.910000 ;
    END
  END VPB

Steps to Reproduce the Problem

  1. Check the .magic.lef file of any cell when you clone any of the submodules.

Specifications

*Note: the purpose of this issue is traceability.

@RTimothyEdwards
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I do not think that "SHAPE ABUTMENT" should be used, because the labels in the LEF are not extending to the cell bounding box edges, so I'm not sure what tools would do with that. The regular power rails abut, which I think should be okay. But if any tool behavior indicates otherwise, I would like to know about it.

@agorararmard
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So far no tool indicated the need for SHAPE ABUTMENT. So, I agree, it shouldn't be added.

@mithro mithro added files-layout-lef-magic Issues related to the Library Exchange Format (LEF) files generated by Magic. lib-sky130_fd_sc_hd Issues with the "high density" digital standard cells provided by the SkyWater foundry. lib-sky130_fd_sc_hdll Issues with the "high density low leakage" digital standard cells provided by the SkyWater foundry. lib-sky130_fd_sc_hs Issues with the "high speed" digital standard cells provided by the SkyWater foundry. lib-sky130_fd_sc_ms Issues with the "medium speed" digital standard cells provided by the SkyWater foundry. lib-sky130_fd_sc_ls Issues with the "low speed" digital standard cells provided by the SkyWater foundry. lib-sky130_fd_sc_lp Issues with the "low power" digital standard cells provided by the SkyWater foundry. lib-sky130_fd_sc_hvl Issues with the "high voltage" digital standard cells provided by the SkyWater foundry. type-bug Something isn't working labels Oct 24, 2020
@mithro
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mithro commented Oct 24, 2020

I'm currently assuming this affects all the sky130_fd_sc_* cells?

@agorararmard
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@mithro: I reviewed the submodules now. The issue exists in sky130_fd_sc_hd, sky130_fd_sc_hdll, and sky130_fd_sc_ls.

So, it doesn't exist in sky130_fd_sc_hs and sky130_fd_sc_ms, sky130_fd_sc_hvl, and sky130_fd_sc_lp

@mithro
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mithro commented Oct 28, 2020

Does this look right?

diff --git a/libraries/sky130_fd_sc_hd/v0.0.1/cells/a22oi/sky130_fd_sc_hd__a22oi_4.magic.lef b/libraries/sky130_fd_sc_hd/v0.0.1/cells/a22oi/sky130_fd_sc_hd__a22oi_4.magic.lef
index 481ecf9..ff1bc43 100644
--- a/libraries/sky130_fd_sc_hd/v0.0.1/cells/a22oi/sky130_fd_sc_hd__a22oi_4.magic.lef
+++ b/libraries/sky130_fd_sc_hd/v0.0.1/cells/a22oi/sky130_fd_sc_hd__a22oi_4.magic.lef
@@ -77,7 +77,7 @@
     END
   END Y
   PIN VGND
-    DIRECTION INPUT ;
+    DIRECTION INOUT ;
     SHAPE ABUTMENT ;
     USE GROUND ;
     PORT
@@ -86,7 +86,7 @@
     END
   END VGND
   PIN VNB
-    DIRECTION INPUT ;
+    DIRECTION INOUT ;
     USE GROUND ;
     PORT
       LAYER pwell ;
@@ -94,7 +94,7 @@
     END
   END VNB
   PIN VPB
-    DIRECTION INPUT ;
+    DIRECTION INOUT ;
     USE POWER ;
     PORT
       LAYER nwell ;
@@ -102,7 +102,7 @@
     END
   END VPB
   PIN VPWR
-    DIRECTION INPUT ;
+    DIRECTION INOUT ;
     SHAPE ABUTMENT ;
     USE POWER ;
     PORT
# Copyright 2020 The SkyWater PDK Authors
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
#     https://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
#
# SPDX-License-Identifier: Apache-2.0

VERSION 5.7 ;
  NOWIREEXTENSIONATPIN ON ;
  DIVIDERCHAR "/" ;
  BUSBITCHARS "[]" ;
MACRO sky130_fd_sc_hd__a22oi_4
  CLASS CORE ;
  FOREIGN sky130_fd_sc_hd__a22oi_4 ;
  ORIGIN  0.000000  0.000000 ;
  SIZE  7.820000 BY  2.720000 ;
  SYMMETRY X Y R90 ;
  SITE unithd ;
  PIN A1
    ANTENNAGATEAREA  0.990000 ;
    DIRECTION INPUT ;
    USE SIGNAL ;
    PORT
      LAYER li1 ;
        RECT 4.275000 1.075000 5.685000 1.285000 ;
    END
  END A1
  PIN A2
    ANTENNAGATEAREA  0.990000 ;
    DIRECTION INPUT ;
    USE SIGNAL ;
    PORT
      LAYER li1 ;
        RECT 5.910000 1.075000 7.735000 1.285000 ;
    END
  END A2
  PIN B1
    ANTENNAGATEAREA  0.990000 ;
    DIRECTION INPUT ;
    USE SIGNAL ;
    PORT
      LAYER li1 ;
        RECT 2.615000 1.075000 4.040000 1.275000 ;
    END
  END B1
  PIN B2
    ANTENNAGATEAREA  0.990000 ;
    DIRECTION INPUT ;
    USE SIGNAL ;
    PORT
      LAYER li1 ;
        RECT 0.090000 1.075000 1.895000 1.275000 ;
    END
  END B2
  PIN Y
    ANTENNADIFFAREA  1.782000 ;
    DIRECTION OUTPUT ;
    USE SIGNAL ;
    PORT
      LAYER li1 ;
        RECT 0.595000 1.445000 3.325000 1.625000 ;
        RECT 0.595000 1.625000 0.805000 2.125000 ;
        RECT 1.395000 1.625000 1.645000 2.125000 ;
        RECT 2.195000 0.645000 5.565000 0.885000 ;
        RECT 2.195000 0.885000 2.445000 1.445000 ;
        RECT 2.235000 1.625000 2.485000 2.125000 ;
        RECT 3.075000 1.625000 3.325000 2.125000 ;
    END
  END Y
  PIN VGND
    DIRECTION INOUT ;
    SHAPE ABUTMENT ;
    USE GROUND ;
    PORT
      LAYER met1 ;
        RECT 0.000000 -0.240000 7.820000 0.240000 ;
    END
  END VGND
  PIN VNB
    DIRECTION INOUT ;
    USE GROUND ;
    PORT
      LAYER pwell ;
        RECT 0.150000 -0.085000 0.320000 0.085000 ;
    END
  END VNB
  PIN VPB
    DIRECTION INOUT ;
    USE POWER ;
    PORT
      LAYER nwell ;
        RECT -0.190000 1.305000 8.010000 2.910000 ;
    END
  END VPB
  PIN VPWR
    DIRECTION INOUT ;
    SHAPE ABUTMENT ;
    USE POWER ;
    PORT
      LAYER met1 ;
        RECT 0.000000 2.480000 7.820000 2.960000 ;
    END
  END VPWR
  OBS
    LAYER li1 ;
      RECT 0.000000 -0.085000 7.820000 0.085000 ;
      RECT 0.000000  2.635000 7.820000 2.805000 ;
      RECT 0.090000  1.455000 0.425000 2.295000 ;
      RECT 0.090000  2.295000 4.265000 2.465000 ;
      RECT 0.095000  0.255000 0.425000 0.725000 ;
      RECT 0.095000  0.725000 2.025000 0.905000 ;
      RECT 0.595000  0.085000 0.765000 0.555000 ;
      RECT 0.935000  0.255000 1.265000 0.725000 ;
      RECT 0.975000  1.795000 1.225000 2.295000 ;
      RECT 1.435000  0.085000 1.605000 0.555000 ;
      RECT 1.775000  0.255000 3.785000 0.475000 ;
      RECT 1.775000  0.475000 2.025000 0.725000 ;
      RECT 1.815000  1.795000 2.065000 2.295000 ;
      RECT 2.655000  1.795000 2.905000 2.295000 ;
      RECT 3.495000  1.455000 7.625000 1.625000 ;
      RECT 3.495000  1.625000 4.265000 2.295000 ;
      RECT 3.975000  0.255000 5.985000 0.475000 ;
      RECT 4.435000  1.795000 4.685000 2.635000 ;
      RECT 4.855000  1.625000 5.105000 2.465000 ;
      RECT 5.275000  1.795000 5.525000 2.635000 ;
      RECT 5.695000  1.625000 5.945000 2.465000 ;
      RECT 5.735000  0.475000 5.985000 0.725000 ;
      RECT 5.735000  0.725000 7.665000 0.905000 ;
      RECT 6.115000  1.795000 6.365000 2.635000 ;
      RECT 6.155000  0.085000 6.325000 0.555000 ;
      RECT 6.495000  0.255000 6.825000 0.725000 ;
      RECT 6.535000  1.625000 6.785000 2.465000 ;
      RECT 6.955000  1.795000 7.205000 2.635000 ;
      RECT 6.995000  0.085000 7.165000 0.555000 ;
      RECT 7.335000  0.255000 7.665000 0.725000 ;
      RECT 7.375000  1.625000 7.625000 2.465000 ;
    LAYER mcon ;
      RECT 0.145000 -0.085000 0.315000 0.085000 ;
      RECT 0.145000  2.635000 0.315000 2.805000 ;
      RECT 0.605000 -0.085000 0.775000 0.085000 ;
      RECT 0.605000  2.635000 0.775000 2.805000 ;
      RECT 1.065000 -0.085000 1.235000 0.085000 ;
      RECT 1.065000  2.635000 1.235000 2.805000 ;
      RECT 1.525000 -0.085000 1.695000 0.085000 ;
      RECT 1.525000  2.635000 1.695000 2.805000 ;
      RECT 1.985000 -0.085000 2.155000 0.085000 ;
      RECT 1.985000  2.635000 2.155000 2.805000 ;
      RECT 2.445000 -0.085000 2.615000 0.085000 ;
      RECT 2.445000  2.635000 2.615000 2.805000 ;
      RECT 2.905000 -0.085000 3.075000 0.085000 ;
      RECT 2.905000  2.635000 3.075000 2.805000 ;
      RECT 3.365000 -0.085000 3.535000 0.085000 ;
      RECT 3.365000  2.635000 3.535000 2.805000 ;
      RECT 3.825000 -0.085000 3.995000 0.085000 ;
      RECT 3.825000  2.635000 3.995000 2.805000 ;
      RECT 4.285000 -0.085000 4.455000 0.085000 ;
      RECT 4.285000  2.635000 4.455000 2.805000 ;
      RECT 4.745000 -0.085000 4.915000 0.085000 ;
      RECT 4.745000  2.635000 4.915000 2.805000 ;
      RECT 5.205000 -0.085000 5.375000 0.085000 ;
      RECT 5.205000  2.635000 5.375000 2.805000 ;
      RECT 5.665000 -0.085000 5.835000 0.085000 ;
      RECT 5.665000  2.635000 5.835000 2.805000 ;
      RECT 6.125000 -0.085000 6.295000 0.085000 ;
      RECT 6.125000  2.635000 6.295000 2.805000 ;
      RECT 6.585000 -0.085000 6.755000 0.085000 ;
      RECT 6.585000  2.635000 6.755000 2.805000 ;
      RECT 7.045000 -0.085000 7.215000 0.085000 ;
      RECT 7.045000  2.635000 7.215000 2.805000 ;
      RECT 7.505000 -0.085000 7.675000 0.085000 ;
      RECT 7.505000  2.635000 7.675000 2.805000 ;
  END
END sky130_fd_sc_hd__a22oi_4
END LIBRARY

@rovinski
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INPUT --> INOUT seems good to me. It is consistent with other PDKs.

@agorararmard
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@mithro: Looks good to me!

@mithro
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mithro commented Oct 29, 2020

@RTimothyEdwards -- What values for the USE / DIRECTION are correct?

@mithro
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mithro commented Oct 29, 2020

mithro added a commit to mithro/skywater-pdk that referenced this issue Oct 29, 2020
Three fixes applied to all standard cell libraries;
 * lef: Fixing VNB/VPB properties in .magic.lef files, fixes google#172.
 * verilog: Fixing power pins usage in non-powerpin mode, fixes google#181.
 * cdl: Fixing missing terminals, fixes google#194.

Updating submodules on 2020-10-29 19:19:47 UTC

 - Updating [`sky130_fd_sc_hd` latest](https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_fd_sc_hd/+/v0.0.2-40-g836b7fa01..v0.0.2-46-g8d095dc6f) to v0.0.2-46-g8d095dc6f
 - Updating [`sky130_fd_sc_hd` v0.0.1](https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_fd_sc_hd/+/v0.0.1-20-g01fde9a43..v0.0.1-23-g3aaa84ef4) to v0.0.1-23-g3aaa84ef4
 - Updating [`sky130_fd_sc_hd` v0.0.2](https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_fd_sc_hd/+/v0.0.2-40-g836b7fa01..v0.0.2-46-g8d095dc6f) to v0.0.2-46-g8d095dc6f
 - Updating [`sky130_fd_sc_hdll` latest](https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_fd_sc_hdll/+/v0.1.1-44-g7abde00cd..v0.1.1-50-g77450af72) to v0.1.1-50-g77450af72
 - Updating [`sky130_fd_sc_hdll` v0.1.0](https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_fd_sc_hdll/+/v0.1.0-22-g05d4cd52..v0.1.0-25-g82ea1266) to v0.1.0-25-g82ea1266
 - Updating [`sky130_fd_sc_hdll` v0.1.1](https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_fd_sc_hdll/+/v0.1.1-44-g7abde00cd..v0.1.1-50-g77450af72) to v0.1.1-50-g77450af72
 - Updating [`sky130_fd_sc_hs` latest](https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_fd_sc_hs/+/v0.0.2-40-gd1e4650c3..v0.0.2-46-g2d165a2ff) to v0.0.2-46-g2d165a2ff
 - Updating [`sky130_fd_sc_hs` v0.0.1](https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_fd_sc_hs/+/v0.0.1-20-ga13469d26..v0.0.1-23-gb81bfbb8d) to v0.0.1-23-gb81bfbb8d
 - Updating [`sky130_fd_sc_hs` v0.0.2](https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_fd_sc_hs/+/v0.0.2-40-gd1e4650c3..v0.0.2-46-g2d165a2ff) to v0.0.2-46-g2d165a2ff
 - Updating [`sky130_fd_sc_ls` latest](https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_fd_sc_ls/+/v0.1.1-42-g26dc99426..v0.1.1-48-gedfe6c90b) to v0.1.1-48-gedfe6c90b
 - Updating [`sky130_fd_sc_ls` v0.1.0](https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_fd_sc_ls/+/v0.1.0-21-gd8c271782..v0.1.0-24-g72e0ddf7a) to v0.1.0-24-g72e0ddf7a
 - Updating [`sky130_fd_sc_ls` v0.1.1](https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_fd_sc_ls/+/v0.1.1-42-g26dc99426..v0.1.1-48-gedfe6c90b) to v0.1.1-48-gedfe6c90b
 - Updating [`sky130_fd_sc_ms` latest](https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_fd_sc_ms/+/v0.0.2-42-gec746c6bf..v0.0.2-48-g175daa5e8) to v0.0.2-48-g175daa5e8
 - Updating [`sky130_fd_sc_ms` v0.0.1](https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_fd_sc_ms/+/v0.0.1-21-ge9d513d1f..v0.0.1-24-ga2ecab114) to v0.0.1-24-ga2ecab114
 - Updating [`sky130_fd_sc_ms` v0.0.2](https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_fd_sc_ms/+/v0.0.2-42-gec746c6bf..v0.0.2-48-g175daa5e8) to v0.0.2-48-g175daa5e8

 * libraries/sky130_fd_sc_hd/latest 836b7fa...8d095dc (3):
   > lef: Fixing VNB/VPB properties in .magic.lef files.
   > verilog: Fixing power pins usage in non-powerpin mode.
   > cdl: Fixing missing terminals.

 * libraries/sky130_fd_sc_hd/v0.0.1 01fde9a...3aaa84e (3):
   > lef: Fixing VNB/VPB properties in .magic.lef files.
   > verilog: Fixing power pins usage in non-powerpin mode.
   > cdl: Fixing missing terminals.

 * libraries/sky130_fd_sc_hd/v0.0.2 836b7fa...8d095dc (3):
   > lef: Fixing VNB/VPB properties in .magic.lef files.
   > verilog: Fixing power pins usage in non-powerpin mode.
   > cdl: Fixing missing terminals.

 * libraries/sky130_fd_sc_hdll/latest 7abde00...77450af (3):
   > lef: Fixing VNB/VPB properties in .magic.lef files.
   > verilog: Fixing power pins usage in non-powerpin mode.
   > cdl: Fixing missing terminals.

 * libraries/sky130_fd_sc_hdll/v0.1.0 05d4cd5...82ea126 (3):
   > lef: Fixing VNB/VPB properties in .magic.lef files.
   > verilog: Fixing power pins usage in non-powerpin mode.
   > cdl: Fixing missing terminals.

 * libraries/sky130_fd_sc_hdll/v0.1.1 7abde00...77450af (3):
   > lef: Fixing VNB/VPB properties in .magic.lef files.
   > verilog: Fixing power pins usage in non-powerpin mode.
   > cdl: Fixing missing terminals.

 * libraries/sky130_fd_sc_hs/latest d1e4650...2d165a2 (3):
   > lef: Fixing VNB/VPB properties in .magic.lef files.
   > verilog: Fixing power pins usage in non-powerpin mode.
   > cdl: Fixing missing terminals.

 * libraries/sky130_fd_sc_hs/v0.0.1 a13469d...b81bfbb (3):
   > lef: Fixing VNB/VPB properties in .magic.lef files.
   > verilog: Fixing power pins usage in non-powerpin mode.
   > cdl: Fixing missing terminals.

 * libraries/sky130_fd_sc_hs/v0.0.2 d1e4650...2d165a2 (3):
   > lef: Fixing VNB/VPB properties in .magic.lef files.
   > verilog: Fixing power pins usage in non-powerpin mode.
   > cdl: Fixing missing terminals.

 * libraries/sky130_fd_sc_ls/latest 26dc994...edfe6c9 (3):
   > lef: Fixing VNB/VPB properties in .magic.lef files.
   > verilog: Fixing power pins usage in non-powerpin mode.
   > cdl: Fixing missing terminals.

 * libraries/sky130_fd_sc_ls/v0.1.0 d8c2717...72e0ddf (3):
   > lef: Fixing VNB/VPB properties in .magic.lef files.
   > verilog: Fixing power pins usage in non-powerpin mode.
   > cdl: Fixing missing terminals.

 * libraries/sky130_fd_sc_ls/v0.1.1 26dc994...edfe6c9 (3):
   > lef: Fixing VNB/VPB properties in .magic.lef files.
   > verilog: Fixing power pins usage in non-powerpin mode.
   > cdl: Fixing missing terminals.

 * libraries/sky130_fd_sc_ms/latest ec746c6...175daa5 (3):
   > lef: Fixing VNB/VPB properties in .magic.lef files.
   > verilog: Fixing power pins usage in non-powerpin mode.
   > cdl: Fixing missing terminals.

 * libraries/sky130_fd_sc_ms/v0.0.1 e9d513d...a2ecab1 (3):
   > lef: Fixing VNB/VPB properties in .magic.lef files.
   > verilog: Fixing power pins usage in non-powerpin mode.
   > cdl: Fixing missing terminals.

 * libraries/sky130_fd_sc_ms/v0.0.2 ec746c6...175daa5 (3):
   > lef: Fixing VNB/VPB properties in .magic.lef files.
   > verilog: Fixing power pins usage in non-powerpin mode.
   > cdl: Fixing missing terminals.

Signed-off-by: Tim 'mithro' Ansell <me@mith.ro>
@mithro
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mithro commented Oct 30, 2020

This should be fixed as #196 is now merged.

mithro added a commit to google/skywater-pdk-libs-sky130_fd_sc_hd that referenced this issue Dec 10, 2020
Both the `PIN VNB` and `PIN VPB` are now marked with `DIRECTION INOUT`.
The `PIN VNB` is marked with `USE GROUND` and the `PIN VPB` is marked
with `USE POWER`.

This should fix the `.magic.lef` file usage with OpenROAD (and hopefully other
tools too).

Fixes google/skywater-pdk#172

Signed-off-by: Tim 'mithro' Ansell <tansell@google.com>
mithro added a commit to google/skywater-pdk-libs-sky130_fd_sc_hd that referenced this issue Dec 10, 2020
Both the `PIN VNB` and `PIN VPB` are now marked with `DIRECTION INOUT`.
The `PIN VNB` is marked with `USE GROUND` and the `PIN VPB` is marked
with `USE POWER`.

This should fix the `.magic.lef` file usage with OpenROAD (and hopefully other
tools too).

Fixes google/skywater-pdk#172

Signed-off-by: Tim 'mithro' Ansell <tansell@google.com>
mithro added a commit to google/skywater-pdk-libs-sky130_fd_sc_hdll that referenced this issue Dec 10, 2020
Both the `PIN VNB` and `PIN VPB` are now marked with `DIRECTION INOUT`.
The `PIN VNB` is marked with `USE GROUND` and the `PIN VPB` is marked
with `USE POWER`.

This should fix the `.magic.lef` file usage with OpenROAD (and hopefully other
tools too).

Fixes google/skywater-pdk#172

Signed-off-by: Tim 'mithro' Ansell <tansell@google.com>
mithro added a commit to google/skywater-pdk-libs-sky130_fd_sc_hdll that referenced this issue Dec 10, 2020
Both the `PIN VNB` and `PIN VPB` are now marked with `DIRECTION INOUT`.
The `PIN VNB` is marked with `USE GROUND` and the `PIN VPB` is marked
with `USE POWER`.

This should fix the `.magic.lef` file usage with OpenROAD (and hopefully other
tools too).

Fixes google/skywater-pdk#172

Signed-off-by: Tim 'mithro' Ansell <tansell@google.com>
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files-layout-lef-magic Issues related to the Library Exchange Format (LEF) files generated by Magic. lib-sky130_fd_sc_hd Issues with the "high density" digital standard cells provided by the SkyWater foundry. lib-sky130_fd_sc_hdll Issues with the "high density low leakage" digital standard cells provided by the SkyWater foundry. lib-sky130_fd_sc_hs Issues with the "high speed" digital standard cells provided by the SkyWater foundry. lib-sky130_fd_sc_hvl Issues with the "high voltage" digital standard cells provided by the SkyWater foundry. lib-sky130_fd_sc_lp Issues with the "low power" digital standard cells provided by the SkyWater foundry. lib-sky130_fd_sc_ls Issues with the "low speed" digital standard cells provided by the SkyWater foundry. lib-sky130_fd_sc_ms Issues with the "medium speed" digital standard cells provided by the SkyWater foundry. type-bug Something isn't working
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