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[DSLX] Add
gate!
builtin to frontend for manual operand gating.
Adds it to the fuzzer generation infrastructure with a flag to toggle emission. Note #469 -- can't currently fuzz through normal `codegen_main` fuzzing path because it appears the block generator is required. (Should understand that better next week.) Also: * Prints fuzzer samples as crashers in the run_fuzz infrastructure, that way if there's a crash e.g. in one of the smoke tests we still have a reproducer available. * Propagates node name to Gate op in IRParser. * Doesn't constant fold the gate op (since this prevents convergence to fixed point in the optimizer). We'll need to figure out if this is the way we want to handle it -- classic difficulty with hints arises, where the hint lives in tension with optimiation opportunities that would defy the hint. PiperOrigin-RevId: 387822924
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package test_module | ||
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fn __test_module__main(p: bits[1], x: bits[32]) -> bits[32] { | ||
ret gate.3: bits[32] = gate(p, x, id=3) | ||
} |
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Original file line number | Diff line number | Diff line change |
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// Copyright 2021 The XLS Authors | ||
// | ||
// Licensed under the Apache License, Version 2.0 (the "License"); | ||
// you may not use this file except in compliance with the License. | ||
// You may obtain a copy of the License at | ||
// | ||
// http://www.apache.org/licenses/LICENSE-2.0 | ||
// | ||
// Unless required by applicable law or agreed to in writing, software | ||
// distributed under the License is distributed on an "AS IS" BASIS, | ||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. | ||
// See the License for the specific language governing permissions and | ||
// limitations under the License. | ||
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fn main(p: bool, x: u32) -> u32 { | ||
gate!(p, x) | ||
} | ||
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#![test] | ||
fn test_main() { | ||
let _ = assert_eq(u32:-1, main(false, u32:-1)); | ||
let _ = assert_eq(u32:0, main(true, u32:-1)); | ||
() | ||
} |
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Original file line number | Diff line number | Diff line change |
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// Copyright 2021 The XLS Authors | ||
// | ||
// Licensed under the Apache License, Version 2.0 (the "License"); | ||
// you may not use this file except in compliance with the License. | ||
// You may obtain a copy of the License at | ||
// | ||
// http://www.apache.org/licenses/LICENSE-2.0 | ||
// | ||
// Unless required by applicable law or agreed to in writing, software | ||
// distributed under the License is distributed on an "AS IS" BASIS, | ||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. | ||
// See the License for the specific language governing permissions and | ||
// limitations under the License. | ||
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// Issue: was causing an optimizer hang -- attempts to constant fold the gate op | ||
// would not converge. | ||
// | ||
// options: {"codegen": false, "codegen_args": null, "convert_to_ir": true, "input_is_dslx": true, "optimize_ir": true, "simulate": false, "simulator": null, "use_jit": true, "use_system_verilog": true} | ||
// args: (); (bits[10]:0x2aa) | ||
// args: (); (bits[10]:0x3ff) | ||
// args: (); (bits[10]:0x2aa) | ||
// args: (); (bits[10]:0x0) | ||
fn main(x0: (), x1: (s10,)) -> (u11, u11, s10, u11, u11, u11) { | ||
let x3: u11 = u11:0x325; | ||
let x4: u11 = gate!((x3) != (x3), x3); | ||
let x5: u11 = clz(x3); | ||
let x6: s10 = (x1)[0]; | ||
let x7: u11 = !(x3); | ||
(x3, x4, x6, x7, x4, x3) | ||
} |
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