ath10k-ct: fwcfg allows configuring dma-burst setting.

Upstream commit: Revert "ath10k: fix DMA related firmware crashes on multiple devices"
broke at least one device:
#153

But, maybe it helped others.  Leave that patch as is for now, but
offer fwcfg override so users can test and modify their system without
having to recompile.

Signed-off-by: Ben Greear <greearb@candelatech.com>

ath10k-5.4/core.c

@@ -1312,6 +1312,12 @@ static int ath10k_fetch_fwcfg_file(struct ath10k *ar)
 				ar->fwcfg.flags |= ATH10K_FWCFG_FWVER;
 			}
 		}
+		else if (strcasecmp(filename, "dma_burst") == 0) {
+			if (kstrtol(val, 0, &t) == 0) {
+				ar->fwcfg.dma_burst = t;
+				ar->fwcfg.flags |= ATH10K_FWCFG_DMA_BURST;
+			}
+		}
 		else if (strcasecmp(filename, "vdevs") == 0) {
 			if (kstrtol(val, 0, &t) == 0) {
 				ar->fwcfg.vdevs = t;

ath10k-5.4/core.h

@@ -1260,6 +1260,7 @@ struct ath10k {
 #define ATH10K_FWCFG_NOBEAMFORM_SU  (1<<15)
 #define ATH10K_FWCFG_CT_STA         (1<<16)
 #define ATH10K_FWCFG_ALLOW_ALL_MCS  (1<<17)
+#define ATH10K_FWCFG_DMA_BURST      (1<<18)
 
 		u32 flags; /* let us know which fields have been set */
 		char calname[100];
@@ -1284,6 +1285,11 @@ struct ath10k {
 		u32 bmiss_vdevs; /* To disable, set to 0 */
 		u32 max_amsdus;
 		u32 allow_all_mcs;
+		u32 dma_burst; /* 0:  64b or maybe 128b or maybe 'raw'.  1:  256b.  I don't have
+				* enough docs to know exactly what this means.  See 76d164f582150fd0259ec0fcbc485470bcd8033e
+				* and the thing that reverts that.  This fwcfg option allows the user to over-ride this
+				* since it seems that 0 works best on some systems and 1 works best on others.
+				*/
 	} fwcfg;
 
 	struct {

ath10k-5.4/wmi.c

@@ -7199,6 +7199,8 @@ static struct sk_buff *ath10k_wmi_op_gen_init(struct ath10k *ar)
 	config.tx_dbg_log_size = __cpu_to_le32(TARGET_TX_DBG_LOG_SIZE);
 	config.num_wds_entries = __cpu_to_le32(TARGET_NUM_WDS_ENTRIES);
 	config.dma_burst_size = __cpu_to_le32(TARGET_DMA_BURST_SIZE);
+	if (ar->fwcfg.flags & ATH10K_FWCFG_DMA_BURST)
+		config.dma_burst_size = cpu_to_le32(ar->fwcfg.dma_burst);
 	config.mac_aggr_delim = __cpu_to_le32(TARGET_MAC_AGGR_DELIM);
 
 	val = TARGET_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK;
@@ -7336,6 +7338,8 @@ static struct sk_buff *ath10k_wmi_10_1_op_gen_init(struct ath10k *ar)
 	config.tx_dbg_log_size = __cpu_to_le32(TARGET_10X_TX_DBG_LOG_SIZE);
 	config.num_wds_entries = __cpu_to_le32(TARGET_10X_NUM_WDS_ENTRIES);
 	config.dma_burst_size = __cpu_to_le32(TARGET_10X_DMA_BURST_SIZE);
+	if (ar->fwcfg.flags & ATH10K_FWCFG_DMA_BURST)
+		config.dma_burst_size = cpu_to_le32(ar->fwcfg.dma_burst);
 	config.mac_aggr_delim = __cpu_to_le32(TARGET_10X_MAC_AGGR_DELIM);
 
 	val = TARGET_10X_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK;
@@ -7451,6 +7455,8 @@ static struct sk_buff *ath10k_wmi_10_2_op_gen_init(struct ath10k *ar)
 	config.tx_dbg_log_size = __cpu_to_le32(TARGET_10X_TX_DBG_LOG_SIZE);
 	config.num_wds_entries = __cpu_to_le32(TARGET_10X_NUM_WDS_ENTRIES);
 	config.dma_burst_size = __cpu_to_le32(TARGET_10_2_DMA_BURST_SIZE);
+	if (ar->fwcfg.flags & ATH10K_FWCFG_DMA_BURST)
+		config.dma_burst_size = cpu_to_le32(ar->fwcfg.dma_burst);
 	config.mac_aggr_delim = __cpu_to_le32(TARGET_10X_MAC_AGGR_DELIM);
 
 	val = TARGET_10X_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK;
@@ -7602,6 +7608,8 @@ static struct sk_buff *ath10k_wmi_10_4_op_gen_init(struct ath10k *ar)
 	config.tx_dbg_log_size  = __cpu_to_le32(TARGET_10_4_TX_DBG_LOG_SIZE);
 	config.num_wds_entries  = __cpu_to_le32(TARGET_10_4_NUM_WDS_ENTRIES);
 	config.dma_burst_size   = __cpu_to_le32(TARGET_10_4_DMA_BURST_SIZE);
+	if (ar->fwcfg.flags & ATH10K_FWCFG_DMA_BURST)
+		config.dma_burst_size = cpu_to_le32(ar->fwcfg.dma_burst);
 	config.mac_aggr_delim   = __cpu_to_le32(TARGET_10_4_MAC_AGGR_DELIM);
 
 	config.rx_skip_defrag_timeout_dup_detection_check =