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ath10k: Support configuring specific bandwidths for 10.1 CT firmware.
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This may help with regulatory testing.

Signed-off-by: Ben Greear <greearb@candelatech.com>
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greearb committed Jul 27, 2017
1 parent a18c86b commit cd1eb5a
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Showing 10 changed files with 88 additions and 17 deletions.
9 changes: 9 additions & 0 deletions ath10k-4.4/core.c
View file
Expand Up @@ -2321,6 +2321,15 @@ int ath10k_core_start(struct ath10k *ar, enum ath10k_firmware_mode mode)
if (ar->eeprom_overrides.wmi_wd_keepalive_ms)
ath10k_wmi_pdev_set_special(ar, SET_SPECIAL_ID_WMI_WD,
ar->eeprom_overrides.wmi_wd_keepalive_ms);
if (ar->eeprom_overrides.ct_pshack)
ath10k_wmi_pdev_set_special(ar, SET_SPECIAL_ID_PSHACK,
ar->eeprom_overrides.ct_pshack);
if (ar->eeprom_overrides.ct_csi)
ath10k_wmi_pdev_set_special(ar, SET_SPECIAL_ID_CSI,
ar->eeprom_overrides.ct_csi);
if (ar->eeprom_overrides.rate_bw_disable_mask)
ath10k_wmi_pdev_set_special(ar, SET_SPECIAL_ID_BW_DISABLE_MASK,
ar->eeprom_overrides.rate_bw_disable_mask);
}

return 0;
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7 changes: 7 additions & 0 deletions ath10k-4.4/core.h
View file
Expand Up @@ -1102,13 +1102,20 @@ struct ath10k {
u8 tx_sta_bw_mask; /* 0: all, 0x1: 20Mhz, 0x2 40Mhz, 0x4 80Mhz */
bool allow_ibss_amsdu;
bool rifs_enable_override;
#define CT_DISABLE_20MHZ 0x1
#define CT_DISABLE_40MHZ 0x2
#define CT_DISABLE_80MHZ 0x4
#define CT_DISABLE_160MHZ 0x8
u16 rate_bw_disable_mask;
u16 max_txpower;
u16 pdev_xretry_th; /* Max failed retries before wifi chip is reset, 10.1 firmware default is 0x40 */
u32 wmi_wd_keepalive_ms; /* 0xFFFFFFFF means disable, otherwise, FW will assert after X ms of not receiving
* a NOP keepalive from the driver. Suggested value is 0xFFFFFFFF, or 8000+.
* 0 means use whatever firmware defaults to (probably 8000).
* Units are actually 1/1024 of a second, but pretty close to ms, at least.
*/
u32 ct_pshack;
u32 ct_csi;
} eeprom_overrides;

/* must be last */
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22 changes: 21 additions & 1 deletion ath10k-4.4/debug.c
View file
Expand Up @@ -2969,6 +2969,21 @@ static ssize_t ath10k_write_ct_special(struct file *file,
if (val == 0xFFFFFFFF)
val = 0; /* 0xFFFFFFFF means disable, FW uses 0 to mean disable */
}
else if (id == SET_SPECIAL_ID_PSHACK) {
ar->eeprom_overrides.ct_pshack = val;
ath10k_warn(ar, "Setting CT-PSHACK override to 0x%x\n", val);
}
else if (id == SET_SPECIAL_ID_CSI) {
ar->eeprom_overrides.ct_csi = val;
ath10k_warn(ar, "Setting CT-CSI dump override to 0x%x\n", val);
}
else if (id == SET_SPECIAL_ID_BW_DISABLE_MASK) {
/* Set bandwidth-disable mask */
ar->eeprom_overrides.rate_bw_disable_mask = val;

ath10k_warn(ar, "Setting pdev rate-bw-disable-mask to 0x%x. Will take effect next time rates are configured.\n",
val);
}
/* Below here are local driver hacks, and not necessarily passed directly to firmware. */
else if (id == 0x1001) {
/* Set station failed-transmit kickout threshold. */
Expand Down Expand Up @@ -3015,10 +3030,15 @@ static ssize_t ath10k_read_ct_special(struct file *file,
"id: 5 Allow-AMSDU-IBSS, 1 enabled, 0 disabled, global setting.\n"
"id: 6 Max TX-Power, 0-65535: Latch max-tx-power, in 0.5 dbM Units.\n"
"id: 7 RC max PER Threshold: 0-256 (50 is default). Tune with Care.\n"
"id: 8 STA-TX-BW-MASK, 0: all, 0x1: 20Mhz, 0x2 40Mhz, 0x4 80Mhz \n"
"id: 8 STA-TX-BW-MASK, 0: all, 0x1: 20Mhz, 0x2 40Mhz, 0x4 80Mhz (station vdevs only)\n"
"id: 9 pdev failed retry threshold, U16, 10.1 firmware default is 0x40\n"
"id: 0xA Enable(1)/Disable(0) baseband RIFS. Default is disabled.\n"
"id: 0xB WMI WD Keepalive(ms): 0xFFFFFFFF disables, otherwise suggest 8000+.\n"
"id: 0xC Power-Save hack: 0x1 ignore PS sleep message from STA\n"
"id: 0x2 mark mcast as 'data-is-buffered' regardless\n"
"id: 0xD Enable CSI reporting for at least probe requests.\n"
"id: 0xE set rate-bandwidth-disable-mask: 20Mhz 0x1, 40Mhz 0x2, 80Mhz 0x4, 160Mhz 0x8.\n"
" Takes effect next time rates are set. Set to 0x0 for default rates.\n"
"\nBelow here are not actually sent to firmware directly, but configure the driver.\n"
"id: 0x1001 set sta-kickout threshold due to tx-failures (0 means disable. Default is 20 * 16.)\n"
"\n";
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20 changes: 13 additions & 7 deletions ath10k-4.4/mac.c
View file
Expand Up @@ -2250,6 +2250,7 @@ static void ath10k_peer_assoc_h_rate_overrides(struct ath10k *ar,
int j;
int hw_rix;
int hw_nss = ar->num_rf_chains;
u16 rate_bw_disable_mask = ar->eeprom_overrides.rate_bw_disable_mask;

if (! test_bit(ATH10K_FW_FEATURE_CT_RATEMASK, ar->fw_features))
return;
Expand All @@ -2264,8 +2265,8 @@ static void ath10k_peer_assoc_h_rate_overrides(struct ath10k *ar,
ratemask = arvif->bitrate_mask.control[band].legacy;
rates = sband->bitrates;

ath10k_warn(ar, "band: %d ratemask: 0x%x hw-nss: %d\n",
band, ratemask, hw_nss);
ath10k_warn(ar, "band: %d ratemask: 0x%x hw-nss: %d rate-bw-disable-mask: 0x%x\n",
band, ratemask, hw_nss, rate_bw_disable_mask);

arg->has_rate_overrides = true;

Expand Down Expand Up @@ -2304,9 +2305,11 @@ static void ath10k_peer_assoc_h_rate_overrides(struct ath10k *ar,
//ath10k_dbg(ar, ATH10K_DBG_MAC,
// "set-enabled, ht: hw-rix: %d, %d i: %d j: %d\n",
// hw_rix, hw_rix + hw_nss * 8, i, j);
ath10k_set_rate_enabled(hw_rix, arg->rate_overrides, 1);
if (!(rate_bw_disable_mask & CT_DISABLE_20MHZ))
ath10k_set_rate_enabled(hw_rix, arg->rate_overrides, 1);
/* Set HT40 rateset too */
ath10k_set_rate_enabled(hw_rix + hw_nss * 8, arg->rate_overrides, 1);
if (!(rate_bw_disable_mask & CT_DISABLE_40MHZ))
ath10k_set_rate_enabled(hw_rix + hw_nss * 8, arg->rate_overrides, 1);
}
}
}
Expand All @@ -2327,11 +2330,14 @@ static void ath10k_peer_assoc_h_rate_overrides(struct ath10k *ar,
//ath10k_dbg(ar, ATH10K_DBG_MAC,
// "set-enabled, vht: hw-rix: %d, %d, %d i: %d j: %d\n",
// hw_rix, hw_rix + hw_nss * 10, hw_rix + hw_nss * 2 * 10, i, j);
ath10k_set_rate_enabled(hw_rix, arg->rate_overrides, 1);
if (!(rate_bw_disable_mask & CT_DISABLE_20MHZ))
ath10k_set_rate_enabled(hw_rix, arg->rate_overrides, 1);
/* Set HT40 rateset too */
ath10k_set_rate_enabled(hw_rix + hw_nss * 10, arg->rate_overrides, 1);
if (!(rate_bw_disable_mask & CT_DISABLE_40MHZ))
ath10k_set_rate_enabled(hw_rix + hw_nss * 10, arg->rate_overrides, 1);
/* Set HT80 rateset too */
ath10k_set_rate_enabled(hw_rix + hw_nss * 2 * 10, arg->rate_overrides, 1);
if (!(rate_bw_disable_mask & CT_DISABLE_80MHZ))
ath10k_set_rate_enabled(hw_rix + hw_nss * 2 * 10, arg->rate_overrides, 1);
}
}
}
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5 changes: 5 additions & 0 deletions ath10k-4.4/wmi.h
View file
Expand Up @@ -6375,6 +6375,11 @@ struct wmi_pdev_set_special_cmd {
#define SET_SPECIAL_ID_PDEV_XRETRY_TH 9 /* Set the threshold for resetting phy due to failed retries, U16 */
#define SET_SPECIAL_ID_RIFS_ENABLE 0xA /* Enable(1)/disable(0) RIFS. Disabled by default. */
#define SET_SPECIAL_ID_WMI_WD 0xB /* Set the watchdog trigger count, 0 means disable */
#define SET_SPECIAL_ID_PSHACK 0xC /* flag 0x1: ignore PS sleep message from STA
* flag 0x2: mark mcast as 'data-is-buffered' regardless.
*/
#define SET_SPECIAL_ID_CSI 0xD /* 0 == disable, else enable reporting CSI data. 10.4 FW only at this time. */
#define SET_SPECIAL_ID_BW_DISABLE_MASK 0xE /* 0x1 == disable 20Mhz, 0x2 == 40Mhz, 0x4 == 80Mhz, 0x8 == 160Mhz. 0x0 == default */


#define CT_CCA_TYPE_MIN0 0
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3 changes: 3 additions & 0 deletions ath10k/core.c
View file
Expand Up @@ -2504,6 +2504,9 @@ int ath10k_core_start(struct ath10k *ar, enum ath10k_firmware_mode mode,
if (ar->eeprom_overrides.ct_csi)
ath10k_wmi_pdev_set_special(ar, SET_SPECIAL_ID_CSI,
ar->eeprom_overrides.ct_csi);
if (ar->eeprom_overrides.rate_bw_disable_mask)
ath10k_wmi_pdev_set_special(ar, SET_SPECIAL_ID_BW_DISABLE_MASK,
ar->eeprom_overrides.rate_bw_disable_mask);
}

return 0;
Expand Down
5 changes: 5 additions & 0 deletions ath10k/core.h
View file
Expand Up @@ -1156,6 +1156,11 @@ struct ath10k {
u8 tx_sta_bw_mask; /* 0: all, 0x1: 20Mhz, 0x2 40Mhz, 0x4 80Mhz */
bool allow_ibss_amsdu;
bool rifs_enable_override;
#define CT_DISABLE_20MHZ 0x1
#define CT_DISABLE_40MHZ 0x2
#define CT_DISABLE_80MHZ 0x4
#define CT_DISABLE_160MHZ 0x8
u16 rate_bw_disable_mask;
u16 max_txpower;
u16 pdev_xretry_th; /* Max failed retries before wifi chip is reset, 10.1 firmware default is 0x40 */
u32 wmi_wd_keepalive_ms; /* 0xFFFFFFFF means disable, otherwise, FW will assert after X ms of not receiving
Expand Down
11 changes: 10 additions & 1 deletion ath10k/debug.c
View file
Expand Up @@ -3003,6 +3003,13 @@ static ssize_t ath10k_write_ct_special(struct file *file,
ar->eeprom_overrides.ct_csi = val;
ath10k_warn(ar, "Setting CT-CSI dump override to 0x%x\n", val);
}
else if (id == SET_SPECIAL_ID_BW_DISABLE_MASK) {
/* Set bandwidth-disable mask */
ar->eeprom_overrides.rate_bw_disable_mask = val;

ath10k_warn(ar, "Setting pdev rate-bw-disable-mask to 0x%x. Will take effect next time rates are configured.\n",
val);
}
/* Below here are local driver hacks, and not necessarily passed directly to firmware. */
else if (id == 0x1001) {
/* Set station failed-transmit kickout threshold. */
Expand Down Expand Up @@ -3049,13 +3056,15 @@ static ssize_t ath10k_read_ct_special(struct file *file,
"id: 5 Allow-AMSDU-IBSS, 1 enabled, 0 disabled, global setting.\n"
"id: 6 Max TX-Power, 0-65535: Latch max-tx-power, in 0.5 dbM Units.\n"
"id: 7 RC max PER Threshold: 0-256 (50 is default). Tune with Care.\n"
"id: 8 STA-TX-BW-MASK, 0: all, 0x1: 20Mhz, 0x2 40Mhz, 0x4 80Mhz \n"
"id: 8 STA-TX-BW-MASK, 0: all, 0x1: 20Mhz, 0x2 40Mhz, 0x4 80Mhz (station vdevs only)\n"
"id: 9 pdev failed retry threshold, U16, 10.1 firmware default is 0x40\n"
"id: 0xA Enable(1)/Disable(0) baseband RIFS. Default is disabled.\n"
"id: 0xB WMI WD Keepalive(ms): 0xFFFFFFFF disables, otherwise suggest 8000+.\n"
"id: 0xC Power-Save hack: 0x1 ignore PS sleep message from STA\n"
"id: 0x2 mark mcast as 'data-is-buffered' regardless\n"
"id: 0xD Enable CSI reporting for at least probe requests.\n"
"id: 0xE set rate-bandwidth-disable-mask: 20Mhz 0x1, 40Mhz 0x2, 80Mhz 0x4, 160Mhz 0x8.\n"
" Takes effect next time rates are set. Set to 0x0 for default rates.\n"
"\nBelow here are not actually sent to firmware directly, but configure the driver.\n"
"id: 0x1001 set sta-kickout threshold due to tx-failures (0 means disable. Default is 20 * 16.)\n"
"\n";
Expand Down
22 changes: 14 additions & 8 deletions ath10k/mac.c
View file
Expand Up @@ -2281,6 +2281,7 @@ static void ath10k_peer_assoc_h_rate_overrides(struct ath10k *ar,
int j;
int hw_rix;
bool ok160 = false;
u16 rate_bw_disable_mask = ar->eeprom_overrides.rate_bw_disable_mask;

/* So, what we really want here is the max number of chains the firmware
* is compiled for. But, since we can have 3x3 firmware run on 2x2 chips,
Expand Down Expand Up @@ -2329,8 +2330,8 @@ static void ath10k_peer_assoc_h_rate_overrides(struct ath10k *ar,
ratemask = arvif->bitrate_mask.control[band].legacy;
rates = sband->bitrates;

ath10k_dbg(ar, ATH10K_DBG_MAC2, "band: %d ratemask: 0x%x hw-nss: %d dev-id: 0x%x\n",
band, ratemask, hw_nss, ar->dev_id);
ath10k_dbg(ar, ATH10K_DBG_MAC2, "band: %d ratemask: 0x%x hw-nss: %d dev-id: 0x%x rate-bw-disable-mask: 0x%x\n",
band, ratemask, hw_nss, ar->dev_id, rate_bw_disable_mask);

arg->has_rate_overrides = true;

Expand Down Expand Up @@ -2369,9 +2370,11 @@ static void ath10k_peer_assoc_h_rate_overrides(struct ath10k *ar,
ath10k_dbg(ar, ATH10K_DBG_MAC2,
"set-enabled, ht: hw-rix: %d, %d i: %d j: %d\n",
hw_rix, hw_rix + hw_nss * 8, i, j);
ath10k_set_rate_enabled(hw_rix, arg->rate_overrides, 1);
if (!(rate_bw_disable_mask & CT_DISABLE_20MHZ))
ath10k_set_rate_enabled(hw_rix, arg->rate_overrides, 1);
/* Set HT40 rateset too */
ath10k_set_rate_enabled(hw_rix + hw_nss * 8, arg->rate_overrides, 1);
if (!(rate_bw_disable_mask & CT_DISABLE_40MHZ))
ath10k_set_rate_enabled(hw_rix + hw_nss * 8, arg->rate_overrides, 1);
}
}
}
Expand Down Expand Up @@ -2409,13 +2412,16 @@ static void ath10k_peer_assoc_h_rate_overrides(struct ath10k *ar,
ath10k_dbg(ar, ATH10K_DBG_MAC2,
"set-enabled, vht: hw-rix-20-40: %d, hw-rix-80: %d orig-hw-rix: %d %d, %d i: %d j: %d\n",
hw_rix_20_40, hw_rix_80, hw_rix, hw_rix + hw_nss * 10, hw_rix + hw_nss * 2 * 10, i, j);
ath10k_set_rate_enabled(hw_rix_20_40, arg->rate_overrides, 1);
if (!(rate_bw_disable_mask & CT_DISABLE_20MHZ))
ath10k_set_rate_enabled(hw_rix_20_40, arg->rate_overrides, 1);
/* Set HT40 rateset too */
ath10k_set_rate_enabled(hw_rix_20_40 + hw_nss * 10, arg->rate_overrides, 1);
if (!(rate_bw_disable_mask & CT_DISABLE_40MHZ))
ath10k_set_rate_enabled(hw_rix_20_40 + hw_nss * 10, arg->rate_overrides, 1);
/* Set HT80 rateset too */
ath10k_set_rate_enabled(hw_rix_80 + hw_nss * 2 * 10, arg->rate_overrides, 1);
if (!(rate_bw_disable_mask & CT_DISABLE_80MHZ))
ath10k_set_rate_enabled(hw_rix_80 + hw_nss * 2 * 10, arg->rate_overrides, 1);
/* And for NICs that support 160Mhz, set those */
if (ok160)
if (ok160 && !(rate_bw_disable_mask & CT_DISABLE_160MHZ))
ath10k_set_rate_enabled(hw_rix + hw_nss * 3 * 10, arg->rate_overrides, 1);
}
}
Expand Down
1 change: 1 addition & 0 deletions ath10k/wmi.h
View file
Expand Up @@ -6555,6 +6555,7 @@ struct wmi_pdev_set_special_cmd {
* flag 0x2: mark mcast as 'data-is-buffered' regardless.
*/
#define SET_SPECIAL_ID_CSI 0xD /* 0 == disable, else enable reporting CSI data. 10.4 FW only at this time. */
#define SET_SPECIAL_ID_BW_DISABLE_MASK 0xE /* 0x1 == disable 20Mhz, 0x2 == 40Mhz, 0x4 == 80Mhz, 0x8 == 160Mhz. 0x0 == default */

#define CT_CCA_TYPE_MIN0 0
#define CT_CCA_TYPE_MIN1 1
Expand Down

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