GitHub - gregani/la16fw: Alternative Logic16 Firmware

Branches Tags

Name		Name	Last commit message	Last commit date
Latest commit History 18 Commits
bin		bin
fx2		fx2
.gitmodules		.gitmodules
LICENSE		LICENSE
Makefile		Makefile
README		README
clock.vhd		clock.vhd
clockmux.vhd		clockmux.vhd
fifo.vhd		fifo.vhd
input_shiftreg.vhd		input_shiftreg.vhd
led.vhd		led.vhd
logic16.xise		logic16.xise
main.ucf		main.ucf
mainmodule.prj		mainmodule.prj
mainmodule.ut		mainmodule.ut
mainmodule.vhd		mainmodule.vhd
mainmodule.xst		mainmodule.xst
sample.vhd		sample.vhd
spi.vhd		spi.vhd
syncflag.vhd		syncflag.vhd
syncsignal.vhd		syncsignal.vhd
test_clockmux.vhd		test_clockmux.vhd
test_fifo.vhd		test_fifo.vhd
test_main.vhd		test_main.vhd
test_mainmodule.vhd		test_mainmodule.vhd
test_sample.vhd		test_sample.vhd

Repository files navigation

There are binaries in the bin directory, so you don't have to build this yourself!

How to build the FX2 firmware:
 * Install SDCC (Small Device C Compiler) to build the FX2 firmware
 * Run "make fx2" to build the fx2 firmware (bin/la16fw-fx2.fw)

How to build the FPGA firmware:
 * Install Xilinx ISE 14.7 Webpack edition to build the FPGA firmware (can be downloaded from http://www.xilinx.com)
 * Run "source path/to/Xilinx/14.7/ISE_DS/settings64.sh" to put Xilinx tools into PATH environment variable etc.
 * Run "make fpga" to build the FPGA firmware (bin/la16fw-fpga-18.bitstream bin/la16fw-fpga-33.bitstream)

How to install the firmware:
 * Run "INSTALL_DIR=/path/to/sigrok-firmware make install"
 * Or copy or link the files from the bin directory to wherever you installed sigrok:
   cp bin/la16fw-fx2.fw /usr/local/share/sigrok-firmware/saleae-logic16-fx2.fw
   cp bin/la16fw-fpga-18.bitstream /usr/local/share/sigrok-firmware/saleae-logic16-fpga-18.bitstream
   cp bin/la16fw-fpga-33.bitstream /usr/local/share/sigrok-firmware/saleae-logic16-fpga-33.bitstream

Notes:
 * The "settings64.sh" from Xilinx modifies the library path such that SDCC doesn't work on my system, so first build the FX2 firmware, then the FPGA part