info.yaml

--- 
# TinyTapeout project information
project:
  wokwi_id:    0        # If using wokwi, set this to your project's ID
  source_files:        # If using an HDL, set wokwi_id as 0 and uncomment and list your source files here. Source files must be in ./src
    - verilog/rtl/top.v
    - verilog/rtl/scanchain.v
    - verilog/blocks/serv/rtl/serv_top.v
    - verilog/blocks/serv/rtl/serv_synth_wrapper.v
    - verilog/blocks/serv/rtl/serv_mem_if.v
    - verilog/blocks/serv/rtl/serv_rf_if.v
    - verilog/blocks/serv/rtl/serv_rf_top.v
    - verilog/blocks/serv/rtl/serv_rf_ram.v
    - verilog/blocks/serv/rtl/serv_rf_ram_if.v
    - verilog/blocks/serv/rtl/serv_alu.v
    - verilog/blocks/serv/rtl/serv_ctrl.v
    - verilog/blocks/serv/rtl/serv_bufreg2.v
    - verilog/blocks/serv/rtl/serv_bufreg.v
    - verilog/blocks/serv/rtl/serv_immdec.v
    - verilog/blocks/serv/rtl/serv_decode.v
    - verilog/blocks/serv/rtl/serv_compdec.v
    - verilog/blocks/serv/rtl/serv_aligner.v
    - verilog/blocks/serv/rtl/serv_state.v
    - verilog/blocks/serv/rtl/serv_csr.v
    - verilog/blocks/serv/servant/servant_arbiter.v
    - verilog/blocks/serv/servant/servant_mux.v
    - verilog/blocks/serv/servant/servant_gpio.v
  top_module:  "gregdavill_serv_top"      # put the name of your top module here, make it unique by prepending your github username

# As everyone will have access to all designs, try to make it easy for someone new to your design to know what
# it does and how to operate it.
#
# Here is an example: https://github.com/mattvenn/tinytapeout_m_segments/blob/main/info.yaml
#
# This info will be automatically collected and used to make a datasheet for the chip.
documentation: 
  author:       "Greg Davill"      # Your name
  discord:      "Greg#9468"      # Your discord handle - make sure to include the # part as well
  title:        "serv"      # Project title
  description:  "An award winning RISCV CPU!"      # Short description of what your project does
  how_it_works: "tbd"      # Longer description of how the project works
  how_to_test:  "tbd"      # Instructions on how someone could test your project, include things like what buttons do what and how to set the clock if needed
  external_hw:  "tbd"      # Describe any external hardware needed
  language:     "verilog" # other examples include Verilog, Amaranth, VHDL, etc
  doc_link:     "tbd"      # URL to longer form documentation, eg the README.md in your repository
  clock_hz:     0       # Clock frequency in Hz (if required) we are expecting max clock frequency to be ~6khz. Provided on input 0.
  picture:      "tbd"      # relative path to a picture in your repository
  inputs:               # a description of what the inputs do
    - clk
    - reset
    - data
    - scan_select
    - serv_clk
  outputs:
    - clk out         # a description of what the outputs do
    - data out