ath79: add cache barrier after register write

Add a cache-barrier after the reset-register write. This fixes spurious
reboot issues on TP-Link WDR3600 and WDR4300 devices with Zental DDR2
DRAM chips.

This issue was fixed in the past, but switching to the reset-driver
specific implementation removed the cache barrier which was previously
implicitly added by reading back the register in question.

Link: freifunk-gluon/gluon#2904
Link: openwrt#13043
Link: https://dev.archive.openwrt.org/ticket/17839

Signed-off-by: David Bauer <mail@david-bauer.net>

target/linux/ath79/patches-5.15/990-reset-ath79-add-cache-barrier-after-register-write.patch

@@ -0,0 +1,38 @@
+From fbc43d5486c39b130fc2f0c26ecc1b95a02e2c59 Mon Sep 17 00:00:00 2001
+From: David Bauer <mail@david-bauer.net>
+Date: Tue, 9 Jan 2024 22:17:37 +0100
+Subject: [PATCH] reset: ath79: add cache barrier after register write
+
+Add a cache-barrier after the reset-register write. This fixes spurious
+reboot issues on TP-Link WDR3600 and WDR4300 devices with Zental DDR2
+DRAM chips.
+
+This issue was fixed in the past, but switching to the reset-driver
+specific implementation removed the cache barrier which was previously
+implicitly added by reading back the register in question.
+
+Link: https://github.com/freifunk-gluon/gluon/issues/2904
+Link: https://github.com/openwrt/openwrt/issues/13043
+Link: https://dev.archive.openwrt.org/ticket/17839
+Link: f8a7bfe1cb2c ("MIPS: ath79: fix system restart")
+
+Signed-off-by: David Bauer <mail@david-bauer.net>
+---
+ drivers/reset/reset-ath79.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/reset/reset-ath79.c b/drivers/reset/reset-ath79.c
+index e48d8fcb3133..fc602925da66 100644
+--- a/drivers/reset/reset-ath79.c
++++ b/drivers/reset/reset-ath79.c
+@@ -37,6 +37,7 @@ static int ath79_reset_update(struct reset_controller_dev *rcdev,
+ 	else
+ 		val &= ~BIT(id);
+ 	writel(val, ath79_reset->base);
++	barrier();
+ 	spin_unlock_irqrestore(&ath79_reset->lock, flags);
+
+ 	return 0;
+-- 
+2.43.0
+