RI5CY: RISC-V Core

RI5CY is a small 4-stage RISC-V core. It starte its life as a fork of the OR10N cpu core that is based on the OpenRISC ISA.

RI5CY fully implements the RV32I instruction set, the multiply instruction from RV32M and many custom instruction set extensions that improve its performance for signal processing applications.

The core was developed as part of the PULP platform for energy-efficient computing and is currently used as the processing core for PULP and PULPino.

Documentation

A datasheet that explains the most important features of the core can be found in docs/datasheet/.

It is written using LaTeX and can be generated as follows

make all

Name		Name	Last commit message	Last commit date
Latest commit History 405 Commits
docs/datasheet		docs/datasheet
include		include
tb/serDiv		tb/serDiv
.gitignore		.gitignore
LICENSE		LICENSE
README.md		README.md
alu.sv		alu.sv
alu_div.sv		alu_div.sv
compressed_decoder.sv		compressed_decoder.sv
controller.sv		controller.sv
cs_registers.sv		cs_registers.sv
debug_unit.sv		debug_unit.sv
decoder.sv		decoder.sv
ex_stage.sv		ex_stage.sv
exc_controller.sv		exc_controller.sv
hwloop_controller.sv		hwloop_controller.sv
hwloop_regs.sv		hwloop_regs.sv
id_stage.sv		id_stage.sv
if_stage.sv		if_stage.sv
load_store_unit.sv		load_store_unit.sv
mult.sv		mult.sv
prefetch_L0_buffer.sv		prefetch_L0_buffer.sv
prefetch_buffer.sv		prefetch_buffer.sv
register_file.sv		register_file.sv
register_file_ff.sv		register_file_ff.sv
riscv_core.sv		riscv_core.sv
riscv_simchecker.sv		riscv_simchecker.sv
riscv_tracer.sv		riscv_tracer.sv
src_files.yml		src_files.yml

License

gwsu/riscv

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RI5CY: RISC-V Core

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