Skip to content

Commit

Permalink
TZXPlayer: add a progressbar overlay
Browse files Browse the repository at this point in the history
  • Loading branch information
@gyurco
gyurco committed Jan 13, 2021
1 parent 047515d commit 27bc47b
Show file tree
Hide file tree
Showing 5 changed files with 137 additions and 7 deletions.
8 changes: 6 additions & 2 deletions Amstrad.qsf
View file
Expand Up @@ -41,7 +41,7 @@ set_global_assignment -name DEVICE EP3C25E144C8
set_global_assignment -name TOP_LEVEL_ENTITY Amstrad
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:48:12 FEBRUARY 22, 2015"
set_global_assignment -name LAST_QUARTUS_VERSION 13.1
set_global_assignment -name LAST_QUARTUS_VERSION "13.1 SP4.26"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
Expand Down Expand Up @@ -285,7 +285,7 @@ set_global_assignment -name SEED 1
set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:build_id_verilog.tcl"
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
set_global_assignment -name ENABLE_SIGNALTAP OFF
set_global_assignment -name USE_SIGNALTAP_FILE output_files/playcity.stp
set_global_assignment -name USE_SIGNALTAP_FILE output_files/progress.stp
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
set_global_assignment -name SMART_RECOMPILE ON
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_HS
Expand All @@ -304,6 +304,7 @@ set_global_assignment -name VERILOG_FILE GA40010/syncgen_sync.v
set_global_assignment -name VERILOG_FILE GA40010/casgen_sync.v
set_global_assignment -name SYSTEMVERILOG_FILE GA40010/video.sv
set_global_assignment -name VERILOG_FILE GA40010/rslatch.v
set_global_assignment -name VERILOG_FILE progressbar.v
set_global_assignment -name VERILOG_FILE crt_filter.v
set_global_assignment -name SYSTEMVERILOG_FILE u765/u765.sv
set_global_assignment -name VERILOG_FILE sdram.v
Expand All @@ -327,4 +328,7 @@ set_global_assignment -name SIGNALTAP_FILE output_files/newga.stp
set_global_assignment -name SIGNALTAP_FILE output_files/cpu.stp
set_global_assignment -name SIGNALTAP_FILE output_files/tzxplayer.stp
set_global_assignment -name SIGNALTAP_FILE output_files/playcity.stp
set_global_assignment -name SIGNALTAP_FILE output_files/progress.stp
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
3 changes: 3 additions & 0 deletions Amstrad.sdc
View file
Expand Up @@ -32,8 +32,11 @@ set_multicycle_path -from {Amstrad_motherboard:motherboard|T80pa:CPU|T80:u0|*} -
set_multicycle_path -to {u765:u765|fdc.i_rpm_time[*][*][*]} -setup 4
set_multicycle_path -to {u765:u765|fdc.i_rpm_time[*][*][*]} -hold 3


# False paths

set_false_path -to {tape_progress[*]}

# Don't bother optimizing sigma_delta_dac
set_false_path -to {sigma_delta_dac:*}

Expand Down
29 changes: 25 additions & 4 deletions Amstrad.sv
View file
Expand Up @@ -370,6 +370,7 @@ end
////////////////////// CDT playback ///////////////////////////////

wire tape_read;
wire tape_running;
wire tape_data_req;
reg tape_data_ack;
reg tape_reset;
Expand Down Expand Up @@ -424,7 +425,27 @@ tzxplayer (
.tzx_req(tape_data_req),
.tzx_ack(tape_data_ack),
.cass_read(tape_read),
.cass_motor(tape_motor)
.cass_motor(tape_motor),
.cass_running(tape_running)
);

wire progress_pix;
reg [31:0] tape_progress;

always @(posedge clk_sys)
if (tape_last_addr != 0)
tape_progress <= tape_play_addr * 7'd127 / tape_last_addr;
else
tape_progress <= 0;

progressbar progressbar(
.clk(clk_sys),
.ce_pix(ce_16),
.HSync(HSync),
.VSync(VSync),
.enable(tape_running),
.progress(tape_progress[6:0]),
.pix(progress_pix)
);

//////////////////////////////////////////////////////////////////////////
Expand Down Expand Up @@ -770,9 +791,9 @@ mist_video #(.SD_HCNT_WIDTH(10), .OSD_X_OFFSET(10'd18)) mist_video (
.blend ( 1'b0 ),

// video in
.R ( blank ? 6'd0 : R[7:2] ),
.G ( blank ? 6'd0 : G[7:2] ),
.B ( blank ? 6'd0 : B[7:2] ),
.R ( blank ? 6'd0 : ( R[7:2] | {6{progress_pix}}) ),
.G ( blank ? 6'd0 : ( G[7:2] | {6{progress_pix}}) ),
.B ( blank ? 6'd0 : ( B[7:2] | {6{progress_pix}}) ),

.HSync ( ~HSync ),
.VSync ( ~VSync ),
Expand Down
100 changes: 100 additions & 0 deletions progressbar.v
View file
@@ -0,0 +1,100 @@
/*
A simple progressbar overlay
*/

module progressbar (
input clk,
input ce_pix,
input HSync,
input VSync,
input enable,
input [6:0] progress, // 0-127
output pix
);

parameter X_OFFSET = 11'd200;
parameter Y_OFFSET = 11'd40;

// *********************************************************************************
// video timing and sync polarity anaylsis
// *********************************************************************************

// horizontal counter
reg [10:0] h_cnt;
reg [10:0] hs_low, hs_high;
wire hs_pol = hs_high < hs_low;

// vertical counter
reg [10:0] v_cnt;
reg [10:0] vs_low, vs_high;
wire vs_pol = vs_high < vs_low;

always @(posedge clk) begin
reg hsD;
reg vsD;

if(ce_pix) begin
// bring hsync into local clock domain
hsD <= HSync;

// falling edge of HSync
if(!HSync && hsD) begin
h_cnt <= 0;
hs_high <= h_cnt;
end

// rising edge of HSync
else if(HSync && !hsD) begin
h_cnt <= 0;
hs_low <= h_cnt;
v_cnt <= v_cnt + 1'd1;
end else begin
h_cnt <= h_cnt + 1'd1;
end

vsD <= VSync;

// falling edge of VSync
if(!VSync && vsD) begin
v_cnt <= 0;
// if the difference is only one line, that might be interlaced picture
if (vs_high != v_cnt + 1'd1) vs_high <= v_cnt;
end

// rising edge of VSync
else if(VSync && !vsD) begin
v_cnt <= 0;
// if the difference is only one line, that might be interlaced picture
if (vs_low != v_cnt + 1'd1) vs_low <= v_cnt;
end
end
end

// area in which OSD is being displayed
wire [10:0] h_osd_start = X_OFFSET;
wire [10:0] h_osd_end = h_osd_start + 8'd132;
wire [10:0] v_osd_start = Y_OFFSET;
wire [10:0] v_osd_end = v_osd_start + 8'd8;

wire [10:0] osd_hcnt = h_cnt - h_osd_start;
wire [3:0] osd_vcnt = v_cnt - v_osd_start;
reg osd_de;
reg osd_pixel;

always @(posedge clk) begin
if(ce_pix) begin
case (osd_vcnt)
0,7: osd_pixel <= 1;
2,3,4,5: osd_pixel <= osd_hcnt == 0 || osd_hcnt == 130 || ((osd_hcnt - 2'd2) < progress);
default: osd_pixel <= osd_hcnt == 0 || osd_hcnt == 130;
endcase

osd_de <=
(HSync != hs_pol) && (h_cnt >= h_osd_start) && ((h_cnt + 1'd1) < h_osd_end) &&
(VSync != vs_pol) && (v_cnt >= v_osd_start) && (v_cnt < v_osd_end);
end
end

assign pix = enable & osd_pixel & osd_de;

endmodule
4 changes: 3 additions & 1 deletion tzxplayer.vhd
View file
Expand Up @@ -42,7 +42,8 @@ port(
stop : out std_logic; -- tape should be stopped
stop48k : out std_logic; -- tape should be stopped in 48k mode
cass_read : out std_logic; -- tape read signal
cass_motor : in std_logic -- 1 = tape motor is powered
cass_motor : in std_logic; -- 1 = tape motor is powered
cass_running : out std_logic -- tape is running
);
end tzxplayer;

Expand Down Expand Up @@ -110,6 +111,7 @@ signal data_len_dword : std_logic_vector(31 downto 0);
begin

cass_read <= wave_period;
cass_running <= playing;
tap_fifo_do <= host_tap_in;
process(clk)
begin
Expand Down

0 comments on commit 27bc47b

Please sign in to comment.