Lab3.tex

\documentclass[12pt, logo=tehranDLDL/ut]{tehranDLDL}
\usepackage{subcaption}
\usepackage{pgfplots}
\usepackage{todonotes}
\usepackage{amsmath}

\suptitle{Experiment 3}
\supsubtitle{Sessions 7, 8}
\title{Function Generator}
\author{Katayoon Basharkhah \& Hadi Safari}
\preparer{Katayoon Basharkhah}
\supervisor{Professor Z. Navabi}
\university{University of Tehran}
\college{College of Engineering\\School of Electrical \& Computer Engineering}
\course[DLLab]{Digital Logic Laboratory}
\coursecode{ECE 045}
\courseurl{https://gitlab.com/hadi_sfr/ut-dldlab/-/jobs/artifacts/master/download?job=build}
\date{Spring 1398}

\graphicspath{{img/3/}}
\pgfplotsset{compat=1.16}

\begin{document}

\maketitle

\tableofcontents
\newpage

\section*{Introduction}
\addcontentsline{toc}{section}{Introduction}

An Arbitrary Generator (AFG) is an electronic test instrument that generates a wide variety of waveforms with different amplitude and frequency. Among them are sine, square, rhomboid, saw-tooth and any arbitrary waveform. You can use AFGs to simply generate a series of basic test signals, replicate real-world signals, or create signals that are not otherwise available. These signals can then be used to learn more about how a circuit works, to characterize an electronic component, and to verify electronic theories.

In this experiment, you are to design an Arbitrary Generator that is capable of generating each of the aforementioned waveforms with wide range for frequency selection. You will make use of the frequency regulator that you have designed in the Experiment~2.

By the end of this experiment, you should have learned:

\begin{itemize}
    \item The principle of function generators
    \item PWM Digital to Analog Converters (DAC)
    \item Using ROM memories in your design
    \item Schematic design in Quartus~II
\end{itemize}

Some specifications are considered for a function generator:
The \textit{bandwidth}, that is the frequency range of the source signal,
the \textit{sample rate}, that is the maximum clock rate of the source signal,
and the \textit{vertical resolution}, the smallest voltage increment that can be programmed in a signal source.Resolution is the data word width, in bits, of the instrument’s DAC.

\begin{figure}[b]
    \centering
    \caption{Block diagram of the Arbitrary Generator (AFG)\label{fig:AFGblockdia}}
    \resizebox{0.9\textwidth}{!}{\input{img/3/AFGblockdia}}
\end{figure}

\Fref{fig:AFGblockdia} shows the simplified block diagram of an arbitrary generator.
Based on these specifications there is
a main component that generates one of the desired waveform based on the function selectors’ value,
a frequency selector that sets the output signal frequency,
an amplitude selector
and a DAC that converts the digital output to an analog signal, which can be observed and evaluated via an oscilloscope.
A ROM memory is usually embedded to store any other arbitrary waveform.

Accordingly, Below is the topics that are explained in the following of this experiment in details:
\begin{itemize}
    \item DAC
    \item Frequency Selector
    \item Waveform Generator
    \item Amplitude Selector
\end{itemize}

\section{Digital to Analog conversion using PWM}

There are different methods for digital to analog conversion. You can either use an external chip like using an add-on-board card that consists of both ADC and DAC or it can be implemented using Pulse Width Modulation (PWM).
\Fref{fig:DACblockdia} shows the DAC circuit. As can be seen for realizing an external DAC chip a serial to parallel interface is required between the FPGA board and the chip. In this experiment, you will use the second method to have a digital to analog conversion. The following is a brief description of how PWM works as a DAC.

\begin{figure}
    \centering
    \caption{Block diagram of Digital to Analog Converter\label{fig:DACblockdia}}
    \resizebox{0.9\textwidth}{!}{\input{img/3/DACblockdia}}
\end{figure}

A PWM signal is a sequence of periods in which the duration of the logic-high (or logic-low) voltage varies according to external conditions, and these variations can be used to transmit information. The PWM carrier frequency is constant, so the active and inactive state duration increase or decrease vice versa. The duty cycle of the PWM signal is equal to:
$$\mathit{duty\ cycle} = \frac{T_\mathit{on}}{T_\mathit{on} + T_\mathit{off}}$$

The nominal DAC voltage observed at the output of the low-pass filter is determined by just two parameters, namely,
the duty cycle and the PWM signal’s logic-high voltage;
in the \fref{fig:PMW}, \textit{A} denotes this logic-high voltage for ``amplitude.''
The relationship between duty cycle, amplitude, and nominal DAC voltage is fairly intuitive:
In the frequency domain, a low-pass filter suppresses higher-frequency components of an input signal. The time-domain equivalent of this effect is smoothing, or averaging. Thus, by low-pass filtering a PWM signal we are extracting its average value.

\begin{figure}
    \centering
    \caption{Pulse Width Modulation (PMW)\label{fig:PMW}}
    \includegraphics[width=0.7\textwidth]{PMW.png}
\end{figure}

Period of PWM has to be small enough so the effect of on/off switching be unnoticeable on load. Pulse Width (PW) determines amount of power that is fed to load.
In this experiment, period of PWM is fixed to 256~clocks and its pulse width is the value on 8-bit input of module.
\Fref{fig:PMW} shows sample PWM waves. In each cycle, first \textit{PW} clock output value is 1 and it is 0 for rest of cycle.

\begin{enumerate}
    \item Write a Verilog code for DAC module. The output of the PWM module will go to an external board with an RC low pass filter.
    \item You can use a random data input from the switches to test the accuracy of your design.
\end{enumerate}

\designverification{}

\section{Frequency Selector}

In order to set the frequency of the output signal a frequency selector (or regulated frequency) is required. The frequency selector consists of a counter that divides a high source input signal to the desired value.
You can take advantage of your previous design of the frequency regulator.
The Block diagram of this component is shown in \fref{fig:FSblockdia}.

\begin{figure}
    \centering
    \caption{Block diagram of frequency selector\label{fig:FSblockdia}}
    \resizebox{0.9\textwidth}{!}{\input{img/3/FSblockdia}}
\end{figure}

Use the frequency divider of the Experiment~1 that implements a ring oscillator as the source signal. In this case, the frequency selector of your function generator will be an external circuit. If you take this option, use dip switches to turn the parallel load inputs on and off.

\designverification{}

\section{Waveform Generator}

This module is the heart of this project. It produces desired functions. Functions generated by this module have the fixed period of 256~clocks. Output of this module is an 8-bit digital representing the amplitude of signal. It should be noted that due to characteristics of implemented DAC, the valid range on output is between $V_\mathit{CC}$ and $\mathit{GND}$. The supported functions, shown in \fref{fig:waveforms}, are rhomboid, sine, square, triangle and saw-tooth.

\begin{figure}
    \centering
    \caption{Different waveforms of function generator\label{fig:waveforms}}
    \includegraphics[width=0.7\textwidth]{waveforms}
\end{figure}

\begin{enumerate}
    \item As shown, waveforms rhomboid, square and triangle are based on a counter that counts up or down with each clock for the period of the waveform. The output of the frequency selector is the input for this module that determines the discrete incremental values of this signal (resolution).
    
    \item Generation of sine function can be somewhat different. The following second order differential equation can be used to generate the sine function:
    \begin{gather*}
    \sin(n) = \sin(n-1) + a.\cos(n-1)\\
    \cos(n) = \cos(n-1) - a.\sin(n)
    \end{gather*}
    
    In order to do the mathematical operations with reasonable accuracy, operations are done in 16-bit fixed point. Also, considering the period of about 256 clock cycles from frequency selector, the equations turn to:
    \begin{gather*}
    \sin(n) = \sin(n-1) + \frac{1}{64}.\cos(n-1)\\
    \cos(n) = \cos(n-1) - \frac{1}{64}.\sin(n)
    \end{gather*}
    Assuming values are between -32768 to 32767 for $\sin$ and $\cos$.

    Initialization of first values in differential equations is necessary. Use $0$ for $\sin(0)$ and $30000$ for $\cos(0)$.
    The results of sine and cosine operations are signed and between -127 to +128. However, for simplification and compatibility with other parts of this experiment, we add an offset of 127, making the range of our signal between 0 and 256. 

    \item To generate the arbitrary, you should use a 1-port ROM memory to store the value of the desired signal at each increment inside the memory addresses. You will receive a file named \path{arbitray.mif} that is used for ROM initialization. 

    \Fref{fig:WGblockdia} shows the block diagram of the waveform generator module.
\end{enumerate}

\begin{figure}
    \centering
    \caption{Block diagram of waveform generator\label{fig:WGblockdia}}
    \resizebox{0.9\textwidth}{!}{\input{img/3/WGblockdia}}
\end{figure}

\Fref{tab:funcsel} shows the order of function selection. These are the control signals for the waveform generator module.
Write the Verilog code for the red box in \fref{fig:WGblockdia} and use LPM or Megawizard functions for ROM memory or Multiplexers.
You will finally get all the components together in a schematic design.

\begin{table}[t]
    \centering
    \caption{Function selection\label{tab:funcsel}}
    \begin{tabular}{c c}
        \texttt{func[2:0]} & Function\\
        \hline
        \texttt{3'b000} & rhomboid\\
        \texttt{3'b001} & sine\\
        \texttt{3'b010} & square\\
        \texttt{3'b011} & triangle\\
        \texttt{3'b100} & saw-tooth\\
        \texttt{3'b101} & arbitrary
    \end{tabular}
\end{table}

\designverification{}

\section{Amplitude Selector}

One option in function generator is the amplitude of generated wave. This can be done by adding a module between digital function generator and DAC. Task of this module is to divide the input taken from digital function generator and divide it by a desired value and feed the result to DAC. Value of divisor is chosen by a 2-bit input.

Type of amplitude is selected by a 2-bit input according to \fref{tab:ampsel}.
\begin{table}[b]
    \centering
    \caption{Amplitude selection\label{tab:ampsel}}
    \begin{tabular}{c c}
        \texttt{ampsel[1:0]} & Amplitude\\
        \hline
        \texttt{2'b00} & 1\\
        \texttt{2'b01} & 2\\
        \texttt{2'b10} & 4\\
        \texttt{2'b11} & 8
    \end{tabular}
\end{table}

\designverification{}

\section{The Total design}

When all the components are designed and verified, you can put them together in a schematic design. Quartus~II has this
capability to generate symbols for any HDL code with the corresponding inputs and outputs. 

\begin{enumerate}
    \item Click on \textit{File $\rhd$ New Project Wizard}.
    \item Create a good directory for your project and complete the form as the previous experiments.
    \item In the \textit{ADD/Remove Files in Project} page add all the Verilog code you have written.
    \item By right click on a Verilog code, you can create a symbol for it. If the symbol generation is done successfully, a file with suffix \path{.bdf} will be generated.
\end{enumerate}

\begin{figure}
    \centering
    \caption{Quartus~II}
    \begin{subfigure}{0.3\textwidth}
        \includegraphics[width=\textwidth]{QuartusII1}
    \end{subfigure}
    ~
    \begin{subfigure}{0.3\textwidth}
        \includegraphics[width=\textwidth]{QuartusII2}
    \end{subfigure}
    ~
    \begin{subfigure}{0.3\textwidth}
        \includegraphics[width=\textwidth]{QuartusII3}
    \end{subfigure}
\end{figure}


You should use bus or line tool from the top toolbar menu \includegraphics[height=2ex]{QuartusII4} and make all the interconnects between components.

Double-click on the blank space in the Graphic Editor window, or click on the icon in the toolbar hat looks like an \texttt{AND} gate. A pop-up box will appear.

Expand the hierarchy in the Libraries box. First expand libraries, then expand the library primitives, followed by expanding the library logic comprises the logic gates. Use the gates if any is needed.

\begin{figure}
    \centering
    \caption{Block diagram in Quartus~II\label{fig:qblockdia}}
    \includegraphics[width=\textwidth]{QuartusII5}
\end{figure}

When the schematic design is completed, compile it as before. Program the design on FPGA and record all the results.

\designverification{}

\section*{Pre-Lab Assignment}
\addcontentsline{toc}{section}{Pre-Lab Assignment}
Before coming to the lab, answer these questions. The pre-lab needs to be handed in at the start of the lab.

\begin{enumerate}
    \item Write a preliminary Verilog code for generating the rhomboid and the sine wave generation.
    \item Draw the datapath of the complete design, including all the input and output signals for each component and also any control signal that you used.
\end{enumerate}


\section*{Acknowledgment}
\addcontentsline{toc}{section}{Acknowledgment}

This lab manual was prepared and developed by \href{mailto:ktbasharkhah@gmail.com?subject=[DLDLab]\%20}{Katayoon Basharkhah}, PHD student of Digital Systems at University of Tehran, under the supervision of professor Zain Navabi.

This manual has been edited by \href{mailto:hadi.safari@ut.ac.ir?subject=[DLDLab]\%20}{Hadi Safari}, undergraduate student of Computer Engineering at University of Tehran.

\end{document}