vhdl

NOTE:

You must have to make a testbench file for executing the code perfectly for reference i have written only for half-adder file you can go for it. Its simple.

Name		Name	Last commit message	Last commit date
Latest commit History 16 Commits
2-bit-comparator		2-bit-comparator
2:1-multiplexer(mux)		2:1-multiplexer(mux)
4:1-mux		4:1-mux
and-nand-gate		and-nand-gate
and-not-gate		and-not-gate
d-flipflop		d-flipflop
demorgan's-2nd-law		demorgan's-2nd-law
demorgan's-ist-law		demorgan's-ist-law
full-adder		full-adder
full-sub		full-sub
half-adder		half-adder
half-sub		half-sub
media		media
nand-gate		nand-gate
nor-gate		nor-gate
not-gate		not-gate
not-nand-gate		not-nand-gate
not-nor-gate		not-nor-gate
or-gate		or-gate
or-nand-gate		or-nand-gate
or-nor-gate		or-nor-gate
sr-flipflop		sr-flipflop
xor-gate		xor-gate
README.md		README.md

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