-
Notifications
You must be signed in to change notification settings - Fork 0
/
register_map.h
193 lines (183 loc) · 4.17 KB
/
register_map.h
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
#include <Arduino.h>
/**
* BMA250E registers
*/
typedef enum : uint8_t
{
REG_CHIP_ID = 0x00,
// 0x01 reserved
REG_ACCD_X_LSB = 0x02,
REG_ACCD_X_MSB = 0x03,
REG_ACCD_Y_LSB = 0x04,
REG_ACCD_Y_MSB = 0x05,
REG_ACCD_Z_LSB = 0x06,
REG_ACCD_Z_MSB = 0x07,
REG_TEMP = 0x08,
REG_INT_STATUS_0 = 0x09,
REG_INT_STATUS_1 = 0x0a,
REG_INT_STATUS_2 = 0x0b,
REG_INT_STATUS_3 = 0x0c,
// 0x0d reserved
REG_FIFO_STATUS = 0x0e,
REG_PMU_RANGE = 0x0f,
REG_PMU_BW = 0x10,
REG_PMU_LPW = 0x11,
REG_PMU_LOW_POWER = 0x12,
REG_ACC_HBW = 0x13,
REG_SOFTRESET = 0x14,
// 0x15 reserved
REG_INT_EN_0 = 0x16,
REG_INT_EN_1 = 0x17,
REG_INT_EN_2 = 0x18,
REG_INT_MAP_0 = 0x19,
REG_INT_MAP_1 = 0x1a,
REG_INT_MAP_2 = 0x1b,
// 0x1c-0x1d reserved
REG_INT_SRC = 0x1e,
// 0x1f reserved
REG_INT_OUT_CTRL = 0x20,
REG_INT_RST_LATCH = 0x21,
REG_INT_0 = 0x22,
REG_INT_1 = 0x23,
REG_INT_2 = 0x24,
REG_INT_3 = 0x25,
REG_INT_4 = 0x26,
REG_INT_5 = 0x27,
REG_INT_6 = 0x28,
REG_INT_7 = 0x29,
REG_INT_8 = 0x2a,
REG_INT_9 = 0x2b,
REG_INT_A = 0x2c,
REG_INT_B = 0x2d,
REG_INT_C = 0x2e,
REG_INT_D = 0x2f,
REG_FIFO_CONFIG_0 = 0x30,
// 0x31 reserved
REG_PMU_SELFTEST = 0x32,
REG_TRIM_NVM_CTRL = 0x33,
REG_SPI3_WDT = 0x34,
// 0x35 reserved
REG_OFC_CTRL = 0x36,
REG_OFC_SETTING = 0x37,
REG_OFC_OFFSET_X = 0x38,
REG_OFC_OFFSET_Y = 0x39,
REG_OFC_OFFSET_Z = 0x3a,
REG_TRIM_GP0 = 0x3b,
REG_TRIM_GP1 = 0x3c,
// 0x3d reserved
REG_FIFO_CONFIG_1 = 0x3e,
REG_FIFO_DATA = 0x3f
} BMA250E_REGS_T;
/**
* PMU_RANGE (accelerometer g-range) values
*/
typedef enum
{
RANGE_2G = 3,
RANGE_4G = 5,
RANGE_8G = 8,
RANGE_16G = 12
} RANGE_T;
/**
* REG_ACC_HBW bits
*/
typedef enum
{
_ACC_HBW_RESERVED_BITS = 0x0f | 0x10 | 0x20,
// 0x01-0x20 reserved
ACC_HBW_SHADOW_DIS = 0x40,
ACC_HBW_DATA_HIGH_BW = 0x80
} ACC_HBW_BITS_T;
/**
* PMU_BW (accelerometer filter bandwidth) values
*/
typedef enum
{
BW_7_81 = 8, // 7.81 Hz
BW_15_63 = 9,
BW_31_25 = 10,
BW_62_5 = 11,
BW_125 = 12,
BW_250 = 13,
BW_500 = 14,
BW_1000 = 15
} BW_T;
/**
* POWER_MODE values
*/
typedef enum
{
POWER_MODE_NORMAL = 0,
POWER_MODE_DEEP_SUSPEND = 1,
POWER_MODE_LOW_POWER = 2,
POWER_MODE_SUSPEND = 4
} POWER_MODE_T;
/**
* REG_PMU_LOW_POWER bits
*/
typedef enum
{
_LOW_POWER_RESERVED_BITS = 0x9F,
// 0x01-0x10 reserved
LOW_POWER_SLEEPTIMER_MODE = 0x20,
LOW_POWER_LOWPOWER_MODE = 0x40 // LPM1 or LPM2 mode. see DS.
// 0x80 reserved
} LOW_POWER_BITS_T;
/**
* REG_PMU_LPW bits
*/
typedef enum
{
// 0x01 reserved
_PMU_LPW_RESERVED_MASK = 0x01,
PMU_LPW_SLEEP_DUR0 = 0x02, // sleep dur in low power mode
PMU_LPW_SLEEP_DUR1 = 0x04,
PMU_LPW_SLEEP_DUR2 = 0x08,
PMU_LPW_SLEEP_DUR3 = 0x10,
_PMU_LPW_SLEEP_MASK = 15,
_PMU_LPW_SLEEP_SHIFT = 1,
// These are separate bits, deep_suspend, lowpower_en and
// suspend (and if all 0, normal). Since only specific
// combinations are allowed, we will treat this as a 3 bit
// bitfield called POWER_MODE.
PMU_LPW_POWER_MODE0 = 0x20, // deep_suspend
PMU_LPW_POWER_MODE1 = 0x40, // lowpower_en
PMU_LPW_POWER_MODE2 = 0x80, // suspend
_PMU_LPW_POWER_MODE_MASK = 7,
_PMU_LPW_POWER_MODE_SHIFT = 5
} PMU_LPW_BITS_T;
/**
* REG_FIFO_CONFIG_1 bits
*/
typedef enum
{
FIFO_CONFIG_1_FIFO_DATA_SEL0 = 0x01,
FIFO_CONFIG_1_FIFO_DATA_SEL1 = 0x02,
_FIFO_CONFIG_1_FIFO_DATA_SEL = 3,
_FIFO_CONFIG_1_FIFO_DATA_SHIFT = 0,
// 0x04-0x20 reserved
FIFO_CONFIG_1_FIFO_MODE0 = 0x40,
FIFO_CONFIG_1_FIFO_MODE1 = 0x80,
_FIFO_CONFIG_1_FIFO_MODE_MASK = 3,
_FIFO_CONFIG_1_FIFO_MODE_SHIFT = 5
} FIFO_CONFIG_1_BITS_T;
/**
* FIFO_DATA_SEL values
*/
typedef enum
{
FIFO_DATA_SEL_XYZ = 0,
FIFO_DATA_SEL_X = 1,
FIFO_DATA_SEL_Y = 2,
FIFO_DATA_SEL_Z = 3
} FIFO_DATA_SEL_T;
/**
* FIFO_MODE values
*/
typedef enum
{
FIFO_MODE_BYPASS = 0,
FIFO_MODE_FIFO = 1,
FIFO_MODE_STREAM = 2
// 3 == reserved (execute self-destruct :)
} FIFO_MODE_T;