board.xml

<?xml version="1.0" encoding="UTF-8" standalone="no"?>
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<board schema_version="2.1" vendor="miner.alinx.com.cn" name="ax7z020" display_name="AX7Z020 Development Board"
       url="https://alinx.com/en/detail/271" preset_file="preset.xml">

    <!-- Image of the board -->
    <images>
        <image name="ac7z020.jpg" display_name="AX7Z020 Development Board" sub_type="board">
            <description>AX7Z020 Development Board</description>
        </image>
    </images>

    <!-- Board PCB revision -->
    <compatible_board_revisions>
        <revision id="1">2.0</revision>
    </compatible_board_revisions>

    <!-- Board file revision -->
    <file_version>1.0</file_version>

    <!-- Board description -->
    <description>
        ALINX AX7021: with an AMD Zynq 7000 SoC XC7Z020 FPGA Development board, “SOM AC7021B system-on-module + Carrier
        Board”, which is convenient to use the SOM core board for secondary development.
        It features embedded processing with Dual ARM Cortex-A9 core processors.
        The AX7021 industrial FPGA board includes all the basic components of hardware, and pre-verified reference
        designs, the carrier board with 5*Gigabit Ethernet, 4*USB2.0, HDMI Output, Uart, SD Card Slot, 40-Pin Connectors
        (expansion opportunities with ALINX Module, such as AD/DA data acquisition module, camera and LCD module). The
        AX7021 FPGA Board is suitable for Multi-port high-speed data transmission, data processing and storage, video
        transmission processing and industrial control, etc.
    </description>
    <components>

        <component name="part0" display_name="AX7Z020" type="fpga" part_name="xc7z020clg400-2"
                   pin_map_file="part0_pins.xml" vendor="xilinx" spec_url="www.xilinx.com">
            <description>FPGA part on the board</description>
            <interfaces>
                <interface mode="master" name="btns_4bits" type="xilinx.com:interface:gpio_rtl:1.0"
                           of_component="btns_4bits" preset_proc="push_buttons_4bits_preset">
                    <port_maps>
                        <port_map logical_port="TRI_I" physical_port="btns_4bits_tri_i" dir="in" left="3" right="0">
                            <pin_maps>
                                <pin_map port_index="0" component_pin="btns_4bits_tri_i_0"/>
                                <pin_map port_index="1" component_pin="btns_4bits_tri_i_1"/>
                                <pin_map port_index="2" component_pin="btns_4bits_tri_i_2"/>
                                <pin_map port_index="3" component_pin="btns_4bits_tri_i_3"/>
                            </pin_maps>
                        </port_map>
                    </port_maps>
                </interface>
                <interface mode="master" name="leds_4bits" type="xilinx.com:interface:gpio_rtl:1.0"
                           of_component="leds_4bits" preset_proc="led_4bits_preset">
                    <port_maps>
                        <port_map logical_port="TRI_O" physical_port="leds_4bits_tri_o" dir="out" left="3" right="0">
                            <pin_maps>
                                <pin_map port_index="0" component_pin="leds_4bits_tri_o_0"/>
                                <pin_map port_index="1" component_pin="leds_4bits_tri_o_1"/>
                                <pin_map port_index="2" component_pin="leds_4bits_tri_o_2"/>
                                <pin_map port_index="3" component_pin="leds_4bits_tri_o_3"/>
                            </pin_maps>
                        </port_map>
                    </port_maps>
                </interface>
                <interface mode="master" name="ps7_fixedio" type="xilinx.com:display_processing_system7:fixedio_rtl:1.0"
                           of_component="ps7_fixedio" preset_proc="ps7_preset">
                </interface>
                <interface mode="slave" name="sys_clock" type="xilinx.com:signal:clock_rtl:1.0" of_component="sys_clock"
                           preset_proc="sys_clock_preset">
                    <port_maps>
                        <port_map logical_port="CLK" physical_port="sys_clk" dir="in">
                            <pin_maps>
                                <pin_map port_index="0" component_pin="sys_clk"/>
                            </pin_maps>
                        </port_map>
                    </port_maps>
                    <parameters>
                        <parameter name="frequency" value="50000000"/>
                    </parameters>
                </interface>


                <interface mode="master" name="hdmi_out" type="digilentinc.com:interface:tmds_rtl:1.0"
                           of_component="hdmi_out">
                    <description>HDMI Out</description>
                    <preferred_ips>
                        <preferred_ip vendor="digilentinc.com" library="ip" name="rgb2dvi" order="0"/>
                    </preferred_ips>
                    <port_maps>
                        <port_map logical_port="CLK_P" physical_port="TMDS_OUT_clk_p" dir="out">
                            <pin_maps>
                                <pin_map port_index="0" component_pin="TMDS_OUT_clk_p"/>
                            </pin_maps>
                        </port_map>
                        <port_map logical_port="CLK_N" physical_port="TMDS_OUT_clk_n" dir="out">
                            <pin_maps>
                                <pin_map port_index="0" component_pin="TMDS_OUT_clk_n"/>
                            </pin_maps>
                        </port_map>
                        <port_map logical_port="DATA_P" physical_port="TMDS_OUT_D_P" dir="out" left="2" right="0">
                            <pin_maps>
                                <pin_map port_index="0" component_pin="TMDS_OUT_data_p_0"/>
                                <pin_map port_index="1" component_pin="TMDS_OUT_data_p_1"/>
                                <pin_map port_index="2" component_pin="TMDS_OUT_data_p_2"/>
                            </pin_maps>
                        </port_map>
                        <port_map logical_port="DATA_N" physical_port="TMDS_OUT_D_N" dir="out" left="2" right="0">
                            <pin_maps>
                                <pin_map port_index="0" component_pin="TMDS_OUT_data_n_0"/>
                                <pin_map port_index="1" component_pin="TMDS_OUT_data_n_1"/>
                                <pin_map port_index="2" component_pin="TMDS_OUT_data_n_2"/>
                            </pin_maps>
                        </port_map>
                    </port_maps>
                </interface>
                <interface mode="master" name="hdmi_out_hpd_led" type="xilinx.com:interface:gpio_rtl:1.0"
                           of_component="hdmi_out_hpd_led" preset_proc="output_1bit_preset">
                    <port_maps>
                        <port_map logical_port="TRI_O" physical_port="hdmi_tx_hpd" dir="out">
                            <pin_maps>
                                <pin_map port_index="0" component_pin="hdmi_tx_hpd"/>
                            </pin_maps>
                        </port_map>
                        <port_map logical_port="TRI_I" physical_port="hdmi_tx_hpd" dir="in">
                            <pin_maps>
                                <pin_map port_index="0" component_pin="hdmi_tx_hpd"/>
                            </pin_maps>
                        </port_map>
                        <port_map logical_port="TRI_T" physical_port="hdmi_tx_hpd" dir="out">
                            <pin_maps>
                                <pin_map port_index="0" component_pin="hdmi_tx_hpd"/>
                            </pin_maps>
                        </port_map>
                    </port_maps>
                </interface>

            </interfaces>
        </component>

        <component name="btns_4bits" display_name="4 Buttons" type="chip" sub_type="push_button" major_group="GPIO">
            <description>Buttons 3 to 0</description>
        </component>

        <component name="leds_4bits" display_name="4 LEDs" type="chip" sub_type="led" major_group="GPIO">
            <description>LEDs 3 to 0</description>
        </component>

        <component name="ps7_fixedio" display_name="ps7_fixedio" type="chip" sub_type="fixed_io" major_group=""/>

        <component name="sys_clock" display_name="System Clock" type="chip" sub_type="system_clock"
                   major_group="Clocks">
            <description>3.3V Single-Ended 50 MHz oscillator used as system clock on the board</description>
        </component>

        <component name="hdmi_out" display_name="HDMI out" type="chip" sub_type="fixed_io" major_group="HDMI">
            <description>HDMI Out (Requires Digilent's TMDS interface)</description>
        </component>

        <component name="hdmi_out_hpd_led" display_name="HDMI out HPD" type="chip" sub_type="led" major_group="HDMI">
            <description>HDMI out HPD</description>
        </component>
    </components>

    <jtag_chains>
        <jtag_chain name="chain1">
            <position name="0" component="part0"/>
        </jtag_chain>
    </jtag_chains>

    <connections>
        <connection name="part0_btns_4bits" component1="part0" component2="btns_4bits">
            <connection_map name="part0_btns_4bits_1" c1_st_index="0" c1_end_index="3" c2_st_index="0"
                            c2_end_index="3"/>
        </connection>

        <connection name="part0_leds_4bits" component1="part0" component2="leds_4bits">
            <connection_map name="part0_leds_4bits_1" c1_st_index="4" c1_end_index="7" c2_st_index="0"
                            c2_end_index="3"/>
        </connection>

        <connection name="part0_sys_clock" component1="part0" component2="sys_clock">
            <connection_map name="part0_sys_clock_1" c1_st_index="8" c1_end_index="8" c2_st_index="0"
                            c2_end_index="0"/>
        </connection>

        <connection name="part0_hdmi_out" component1="part0" component2="hdmi_out">
            <connection_map name="part0_hdmi_out_1" c1_st_index="19" c1_end_index="26" c2_st_index="0"
                            c2_end_index="7"/>
        </connection>

        <connection name="part0_hdmi_out_hpd_led" component1="part0" component2="hdmi_out_hpd_led">
            <connection_map name="part0_hdmi_out_hpd_led_1" c1_st_index="22" c1_end_index="22" c2_st_index="0"
                            c2_end_index="0"/>
        </connection>
    </connections>
</board>