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PD #96169: hdmitx: update hpll setting
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Squashed commit of the following:

commit 0fa46efbdb1eae9771c3d5cf9b1f558ac725301f
Author: zongdong.jiao <zongdong.jiao@amlogic.com>
Date:   Fri Oct 10 21:37:53 2014 +0800

    PD #96169: hdmitx: update hpll setting

commit 795cefa28525f39e6ba5a8f113caf4f01f6466ba
Author: zongdong.jiao <zongdong.jiao@amlogic.com>
Date:   Fri Oct 10 21:37:10 2014 +0800

    PD #96169: hdmitx: merge 97042 commit to a single commit

Conflicts:

	drivers/amlogic/display/vout/enc_clk_config.c

Change-Id: Ib5ad1cc6bd390eeba093eb6b34fc256de470b595
Signed-off-by: Dongjin Kim <tobetter@gmail.com>
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tobetter committed May 22, 2015
1 parent a761439 commit 6b290b1
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Showing 5 changed files with 167 additions and 192 deletions.
1 change: 1 addition & 0 deletions arch/arm/mach-meson8/hdmi_tx_hw/hdmi_tx_hw.c
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Original file line number Diff line number Diff line change
Expand Up @@ -2861,6 +2861,7 @@ static void cts_test(hdmitx_dev_t* hdmitx_device)
printk("dis: %d [%d] %d [%d] %d\n", cts_buf[i].val - cts_buf[i-1].val, i, cts_buf[i].val, i - 1, cts_buf[i - 1].val);
}

min = max = cts_buf[0].val;
for(i = 0; i < AUD_CTS_LOG_NUM; i++) {
total += cts_buf[i].val;
if(min > cts_buf[i].val)
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107 changes: 90 additions & 17 deletions arch/arm/mach-meson8b/hdmi_tx_hw/hdmi_tx_hw.c
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Original file line number Diff line number Diff line change
Expand Up @@ -1474,21 +1474,29 @@ void hdmi_hw_init(hdmitx_dev_t* hdmitx_device)
delay_us(10);
}

#ifdef CONFIG_ARCH_MESON6
// TODO, need test in m8
// When 1080p50hz output, we shall manually configure
// When have below format output, we shall manually configure
// bolow register to get stable Video Timing.
static void hdmi_reconfig_packet_setting(void)
static void hdmi_reconfig_packet_setting(HDMI_Video_Codes_t vic)
{
hdmi_wr_reg(TX_PACKET_ALLOC_ACTIVE_1, 0x01);
hdmi_wr_reg(TX_PACKET_ALLOC_ACTIVE_2, 0x12);
hdmi_wr_reg(TX_PACKET_ALLOC_EOF_1, 0x10);
hdmi_wr_reg(TX_PACKET_ALLOC_EOF_2, 0x12);
hdmi_wr_reg(TX_PACKET_ALLOC_SOF_1, 0xb6);
hdmi_wr_reg(TX_PACKET_ALLOC_SOF_2, 0x11);
hdmi_wr_reg(TX_PACKET_CONTROL_1, (hdmi_rd_reg(TX_PACKET_CONTROL_1)) | (1 << 7)); // bit[7]: forced_packet_timing
switch(vic) {
case HDMI_1080p50:
hdmi_wr_reg(TX_PACKET_CONTROL_1, 0x3a); //0x7e
hdmi_wr_reg(TX_PACKET_ALLOC_ACTIVE_1, 0x01); //0x78
hdmi_wr_reg(TX_PACKET_ALLOC_ACTIVE_2, 0x12); //0x79
hdmi_wr_reg(TX_PACKET_ALLOC_EOF_1, 0x10); //0x7a
hdmi_wr_reg(TX_PACKET_ALLOC_EOF_2, 0x12); //0x7b
hdmi_wr_reg(TX_CORE_ALLOC_VSYNC_0, 0x01); //0x81
hdmi_wr_reg(TX_CORE_ALLOC_VSYNC_1, 0x00); //0x82
hdmi_wr_reg(TX_CORE_ALLOC_VSYNC_2, 0x0a); //0x83
hdmi_wr_reg(TX_PACKET_ALLOC_SOF_1, 0xb6); //0x7c
hdmi_wr_reg(TX_PACKET_ALLOC_SOF_2, 0x11); //0x7d
hdmi_wr_reg(TX_PACKET_CONTROL_1, 0xba); //0x7e
break;
default:
break;
}
printk("reconfig packet setting done\n");
}
#endif

static void hdmi_hw_reset(hdmitx_dev_t* hdmitx_device, Hdmi_tx_video_para_t *param)
{
Expand Down Expand Up @@ -1842,11 +1850,7 @@ static void hdmi_hw_reset(hdmitx_dev_t* hdmitx_device, Hdmi_tx_video_para_t *par
hdmi_wr_reg(TX_SYS5_TX_SOFT_RESET_2, 0x00);
}
}
#ifdef CONFIG_ARCH_MESON6 //todo
if(param->VIC == HDMI_1080p50) {
hdmi_reconfig_packet_setting(); // For 1080p50hz only
}
#endif
hdmi_reconfig_packet_setting(param->VIC);
}

static void hdmi_audio_init(unsigned char spdif_flag)
Expand Down Expand Up @@ -3012,6 +3016,71 @@ static void hdmitx_print_info(hdmitx_dev_t* hdmitx_device, int printk_flag)
hdmi_print(INF, "------------------\n");
}

typedef struct {
unsigned int val : 20;
unsigned int stable: 1;
}aud_cts_log_t;

static inline unsigned int get_msr_cts(void)
{
unsigned int ret;

ret = hdmi_rd_reg(TX_TMDS_ST_CLOCK_METER_1);
ret += (hdmi_rd_reg(TX_TMDS_ST_CLOCK_METER_2) << 8);
ret += ((hdmi_rd_reg(TX_TMDS_ST_CLOCK_METER_3) & 0xf) << 16);

return ret;
}

static inline unsigned int get_msr_cts_st(void)
{
return !!(hdmi_rd_reg(TX_TMDS_ST_CLOCK_METER_3) & 0x80);
}

#define AUD_CTS_LOG_NUM 1000
aud_cts_log_t cts_buf[AUD_CTS_LOG_NUM];
static void cts_test(hdmitx_dev_t* hdmitx_device)
{
int i, j;
unsigned int min = 0, max = 0, total = 0;

printk("\nhdmitx: audio: cts test\n");
memset(cts_buf, 0, sizeof(cts_buf));
for(i = 0; i < AUD_CTS_LOG_NUM; i++) {
cts_buf[i].val = get_msr_cts();
cts_buf[i].stable = get_msr_cts_st();
mdelay(1);
}

printk("cts unstable:\n");
for(i = 0, j = 0; i < AUD_CTS_LOG_NUM; i++) {
if(cts_buf[i].stable == 0) {
printk("%d ", i);
j ++;
if(((j+1) & 0xf) == 0)
printk("\n");
}
}

printk("\ncts change:\n");
for(i = 1; i < AUD_CTS_LOG_NUM; i++) {
if(cts_buf[i].val > cts_buf[i-1].val)
printk("dis: +%d [%d] %d [%d] %d\n", cts_buf[i].val - cts_buf[i-1].val, i, cts_buf[i].val, i - 1, cts_buf[i - 1].val);
if(cts_buf[i].val < cts_buf[i-1].val)
printk("dis: %d [%d] %d [%d] %d\n", cts_buf[i].val - cts_buf[i-1].val, i, cts_buf[i].val, i - 1, cts_buf[i - 1].val);
}

min = max = cts_buf[0].val;
for(i = 0; i < AUD_CTS_LOG_NUM; i++) {
total += cts_buf[i].val;
if(min > cts_buf[i].val)
min = cts_buf[i].val;
if(max < cts_buf[i].val)
max = cts_buf[i].val;
}
printk("\nCTS Min: %d Max: %d Avg: %d/1000\n\n", min, max, total);
}

static void hdmitx_debug(hdmitx_dev_t* hdmitx_device, const char* buf)
{
char tmpbuf[128];
Expand All @@ -3027,6 +3096,10 @@ static void hdmitx_debug(hdmitx_dev_t* hdmitx_device, const char* buf)
hdmitx_dump_tvenc_reg(hdmitx_device->cur_VIC, 1);
return;
}
else if(strncmp(tmpbuf, "ctstest", 7) == 0) {
cts_test(hdmitx_device);
return;
}
else if(strncmp(tmpbuf, "ss", 2) == 0) {
printk("hdmitx_device->output_blank_flag: 0x%x\n", hdmitx_device->output_blank_flag);
printk("hdmitx_device->hpd_state: 0x%x\n", hdmitx_device->hpd_state);
Expand Down
3 changes: 3 additions & 0 deletions arch/arm/mach-meson8b/include/mach/hdmi_tx_reg.h
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Original file line number Diff line number Diff line change
Expand Up @@ -222,6 +222,9 @@ typedef struct {
#define TX_CORE_CALIB_VALUE TX_BASE_ADDR+0x0F7

#define TX_CORE_EDID_CONFIG_MORE TX_BASE_ADDR+0x080
#define TX_CORE_ALLOC_VSYNC_0 TX_BASE_ADDR+0x081
#define TX_CORE_ALLOC_VSYNC_1 TX_BASE_ADDR+0x082
#define TX_CORE_ALLOC_VSYNC_2 TX_BASE_ADDR+0x083

// HDCP shadow register
#define TX_HDCP_SHW_BKSV_0 TX_BASE_ADDR+0x100
Expand Down
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