Sayma: move SAWG logic to separate CD with reset controlled by kernels.

artiq/gateware/rtio/phy/sawg.py

@@ -8,7 +8,7 @@
 
 _Phy = namedtuple("Phy", "rtlink probes overrides")
 
-_ChannelPHY = ClockDomainsRenamer("rio_phy")(_Channel)
+_ChannelPHY = ClockDomainsRenamer("wtf")(_Channel)
 
 
 class Channel(_ChannelPHY):

artiq/gateware/targets/sayma_amc.py

@@ -5,6 +5,7 @@
 import warnings
 
 from migen import *
+from migen.genlib.resetsync import AsyncResetSynchronizer
 
 from misoc.cores import gpio
 from misoc.integration.soc_sdram import soc_sdram_args, soc_sdram_argdict
@@ -114,10 +115,14 @@ def __init__(self):
         self.submodules += serwb_core
         self.add_wb_slave(self.mem_map["serwb"], 8192, serwb_core.etherbone.wishbone.bus)
 
+class just_wtf_crg(Module, AutoCSR):
+    def __init__(self, platform):
+        self.reset = CSRStorage(reset=1)
 
 class Standalone(MiniSoC, AMPSoC, RTMCommon):
     mem_map = {
         "cri_con":       0x10000000,
+        "wtf_crg":       0x10100000,
         "rtio":          0x11000000,
         "rtio_dma":      0x12000000,
         "serwb":         0x13000000,
@@ -206,6 +211,15 @@ def __init__(self, with_sawg, **kwargs):
             self.rtio_core.coarse_ts, self.ad9154_crg.jref)
         self.csr_devices.append("sysref_sampler")
 
+        # Add new CD for SAWG
+        self.submodules.wtf_crg = wtf_crf = just_wtf_crg(platform)
+        self.register_kernel_cpu_csrdevice("wtf_crg")
+
+        self.clock_domains.cd_wtf = ClockDomain()
+        self.comb += self.cd_wtf.clk.eq(ClockSignal("jesd"))
+        self.specials += AsyncResetSynchronizer(self.cd_wtf, wtf_crf.reset.storage)
+
+
         # blinker
         blink_counter = Signal(28)
         blink = Signal()