Sayma: bypass dividers where possible to minimize noise (nb this chan…

…ges the output skew).
hartytp · Jun 12, 2018 · c8935f7 · c8935f7
1 parent 7a0140e
commit c8935f7
Showing 1 changed file with 5 additions and 2 deletions.
diff --git a/artiq/firmware/libboard_artiq/hmc830_7043.rs b/artiq/firmware/libboard_artiq/hmc830_7043.rs
@@ -288,8 +288,11 @@ pub mod hmc7043 {
             write(channel_base + 0x3, aphase & 0x1f);
             write(channel_base + 0x4, dphase & 0x1f);
 
-            // No analog phase shift on clock channels
-            if (channel % 2) == 0 { write(channel_base + 0x7, 0x00); }
+            // bypass analog phase shift on clock channels to reduce noise
+            if (channel % 2) == 0 {
+                if divider != 0 { write(channel_base + 0x7, 0x00); }  // enable divider
+                else  { write(channel_base + 0x7, 0x03); } // bypass divider for lowest noise
+            }
             else { write(channel_base + 0x7, 0x01); }
 
             write(channel_base + 0x8, 0x08)