Dwc2 interrupts (based on #2050) #2584
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This is needed in order to always be able to fit a packet in the fifo. Writing to the fifo is done from an interrupts that fires when the fifo is half-empty, so the fifo must be twice the packet size.
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For 5ade917 I think it's better to double Tx fifo size only for port who has 4096b buffer. As Rx buffer size is already doubled, port with 1280b buffer has very limited usable space. Also 1280b port running in FS doesn't need much performance. |
I think you are right on this, now thinking a bit more, even with 4096, having an in + out with 512 can take up to 2K if we double both of them. It is probalby just better to change tx fifo from half-empty to ful-empty level instead. PS: in the future we may introduce option to select half-empty or 2x fifo size for throughput for application where there is only a few endpoints and want to maximize fifo usage. |
Describe the PR
based on and supersede #2050, since 2050 does not allow maintainer to push update.
history log is reserved, once this is merged, 2050 is marked as merged as well.