Add synthesis / STA support for multiple liberty files.

dependency_support/com_google_skywater_pdk/build_defs.bzl

@@ -97,7 +97,7 @@ def _skywater_cell_library_impl(ctx):
             runfiles = ctx.runfiles(default_lib_depset),
         ),
         StandardCellInfo(
-            corners = corners,
+            corners = corners.values(),
             default_corner = default_corner,
             open_road_configuration = open_road_configuration,
             tech_lef = tech_lef,

static_timing/build_defs.bzl

@@ -14,7 +14,7 @@
 
 """Rules for running openSTA on synthesized Verilog."""
 
-load("//synthesis:build_defs.bzl", "SynthesisInfo")
+load("//third_party/bazel_rules_hdl/synthesis:build_defs.bzl", "SynthesisInfo")
 
 def _run_opensta_impl(ctx):
     """Implementation of the 'run_opensta' rule.
@@ -29,7 +29,8 @@ def _run_opensta_impl(ctx):
     synth_info = ctx.attr.synth_target[SynthesisInfo]
 
     netlist = synth_info.synthesized_netlist
-    liberty_file = synth_info.standard_cell_info.default_corner.liberty
+    default_liberty_file = synth_info.standard_cell_info.default_corner.liberty
+    additional_liberty_files = [corner.liberty for corner in synth_info.standard_cell_info.corners]
 
     (tool_inputs, input_manifests) = ctx.resolve_tools(tools = [ctx.attr._opensta])
     opensta_runfiles_dir = ctx.executable._opensta.path + ".runfiles"
@@ -41,13 +42,14 @@ def _run_opensta_impl(ctx):
         "NETLIST": netlist.path,
         "TOP": synth_info.top_module,
         "LOGFILE": sta_log.path,
-        "LIBERTY": liberty_file.path,
-        "TCL_LIBRARY": opensta_runfiles_dir + "/tk_tcl/library",
+        "LIBERTY": default_liberty_file.path,
+        "ADDITIONAL_LIBERTIES": ",".join([f.path for f in additional_liberty_files]),
+        "TCL_LIBRARY": opensta_runfiles_dir + "/google3/third_party/tcl_tk/libs/library",
     }
 
     ctx.actions.run(
         outputs = [sta_log],
-        inputs = tool_inputs.to_list() + [liberty_file, sta_tcl, netlist],
+        inputs = tool_inputs.to_list() + [default_liberty_file, sta_tcl, netlist] + additional_liberty_files,
         arguments = ["-exit", sta_tcl.path],
         executable = ctx.executable._opensta,
         tools = tool_inputs,

synthesis/build_defs.bzl

@@ -90,6 +90,7 @@ def _synthesize_design_impl(ctx):
         output_file_name = ctx.attr.output_file_name
     output_file = ctx.actions.declare_file(output_file_name)
     default_liberty_file = ctx.attr.standard_cells[StandardCellInfo].default_corner.liberty
+    additional_liberty_files = [corner.liberty for corner in ctx.attr.standard_cells[StandardCellInfo].corners]
 
     synth_tcl = ctx.file.synth_tcl
     abc_script = ctx.file.abc_script
@@ -103,6 +104,8 @@ def _synthesize_design_impl(ctx):
     inputs.append(synth_tcl)
     inputs.append(abc_script)
     inputs.append(default_liberty_file)
+    inputs.extend(additional_liberty_files)
+
 
     (tool_inputs, input_manifests) = ctx.resolve_tools(tools = [ctx.attr.yosys_tool])
 
@@ -137,6 +140,7 @@ def _synthesize_design_impl(ctx):
         "TOP": ctx.attr.top_module,
         "OUTPUT": output_file,
         "LIBERTY": default_liberty_file,
+        "ADDITIONAL_LIBERTIES": additional_liberty_files,
         "DONT_USE_ARGS": dont_use_args,
         "ABC_SCRIPT": abc_script,
         "CONSTR": constr,
@@ -165,6 +169,8 @@ def _synthesize_design_impl(ctx):
     for k, v in script_env_files.items():
         if type(v) == "File":
             env[k] = v.path
+        elif type(v) == "list" and all([type(f) == "File" for f in v]):
+            env[k] = ",".join([f.path for f in v])  # List of File to comma-joined file paths.
         else:
             env[k] = v