Add/support VHDL

[mithro]

Create good support for VHDL.

[mithro]

@umarcor -- This is your cup of tea, right?

[umarcor]

It is. It's as "simple" as providing GHDL (for simulation) plus ghdl-yosys-plugin for synthesis and formal verification. Hence, this issue depends on #2 (Yosys) and #9 (Symbiyosys). For mixed-language simulation, it can be combined with Verilator (#5): ghdl/ghdl#1512 (comment).

[solsjo]

Hi!

Stumbled on this issue and wondered if it could be of help.

I wrote Bazel rules for vunit and ghdl, albeit only for simulation, not for synthesis. It builds ghdl from source but is dependent on llvm and gnat.

rules_ghdl

Though I don't have a gut feeling for the work needed to integrate with ghdl yosys.

Just thought it might be of interest.

[mithro]

@solsjo - It would be great to add this to this repo even if only for simulation.