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Add support for the pl031, a popular RTC chip used by many devices, including qemu-virt. Signed-off-by: Pedro Falcato <pedro.falcato@gmail.com>
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@@ -25,3 +25,4 @@ CONFIG_RTL8168=y | |
CONFIG_RISCV=n | ||
CONFIG_ARM64=y | ||
CONFIG_SERIAL_PL011=y | ||
CONFIG_PL031_RTC=y |
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@@ -1,2 +1,3 @@ | ||
obj-$(CONFIG_X86)+= drivers/rtc/rtc.o | ||
obj-$(CONFIG_GOLDFISH_RTC)+= drivers/rtc/goldfish-rtc.o | ||
obj-$(CONFIG_PL031_RTC)+= drivers/rtc/pl031-rtc.o |
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/* | ||
* Copyright (c) 2023 Pedro Falcato | ||
* This file is part of Onyx, and is released under the terms of the MIT License | ||
* check LICENSE at the root directory for more information | ||
* | ||
* SPDX-License-Identifier: MIT | ||
*/ | ||
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#include <onyx/clock.h> | ||
#include <onyx/dev.h> | ||
#include <onyx/device_tree.h> | ||
#include <onyx/types.h> | ||
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#include <onyx/hwregister.hpp> | ||
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#define RTC_DR 0x0 | ||
#define RTC_LR 0x8 | ||
#define RTC_CR 0x0c | ||
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class pl031_dev | ||
{ | ||
private: | ||
dev_resource *rsrc_; | ||
unsigned int irq_; | ||
hw_range range_; | ||
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public: | ||
pl031_dev(dev_resource *io, unsigned int irq) : rsrc_{io}, irq_{irq}, range_{rsrc_} | ||
{ | ||
} | ||
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int init(); | ||
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u64 get_time() | ||
{ | ||
return range_.read32(RTC_DR); | ||
} | ||
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int set_time(u64 time_epoch) | ||
{ | ||
if (time_epoch > UINT32_MAX) | ||
{ | ||
printf("pl031: The device does not support 64-bit time (tried to set time=%lx)\n", | ||
time_epoch); | ||
return -EIO; | ||
} | ||
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range_.write32(RTC_LR, (u32) time_epoch); | ||
return 0; | ||
} | ||
}; | ||
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#define RTC_CR_START (1 << 0) | ||
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int pl031_dev::init() | ||
{ | ||
if (!range_.init(rsrc_)) | ||
return -ENOMEM; | ||
printf("pl031: initializing...\n"); | ||
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if (!(range_.read32(RTC_CR) & RTC_CR_START)) | ||
{ | ||
// We must only write the RTC start bit | ||
// *IF* it is not started already, else we reset the clock. | ||
range_.write32(RTC_CR, RTC_CR_START); | ||
} | ||
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struct clock_time clk; | ||
clk.epoch = get_time(); | ||
clk.measurement_timestamp = clocksource_get_time(); | ||
time_set(CLOCK_REALTIME, &clk); | ||
return 0; | ||
} | ||
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int pl031_dt_probe(device *fake_dev) | ||
{ | ||
auto dev = (device_tree::node *) fake_dev; | ||
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// Find IRQ, IO resources | ||
auto irq_rc = dev->get_resource(DEV_RESOURCE_FLAG_IRQ); | ||
if (!irq_rc) | ||
return -1; | ||
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auto iorsrc = dev->get_resource(DEV_RESOURCE_FLAG_MEM | DEV_RESOURCE_FLAG_IO_PORT); | ||
if (!iorsrc) | ||
return -1; | ||
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unique_ptr<pl031_dev> gdev = | ||
make_unique<pl031_dev>(iorsrc, static_cast<uint16_t>(irq_rc->start())); | ||
if (!gdev) | ||
return -ENOMEM; | ||
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if (int st = gdev->init(); st < 0) | ||
return st; | ||
gdev.release(); | ||
return 0; | ||
} | ||
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static const char *pl031_compatible_ids[] = {"arm,pl031", nullptr}; | ||
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static driver pl031_driver = { | ||
.name = "pl031", | ||
.devids = pl031_compatible_ids, | ||
.probe = pl031_dt_probe, | ||
.bus_type_node = &pl031_driver, | ||
}; | ||
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int pl031_dt_init() | ||
{ | ||
device_tree::register_driver(&pl031_driver); | ||
return 0; | ||
} | ||
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DRIVER_INIT(pl031_dt_init); |