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db
db
 
 
incremental_db
incremental_db
 
 
output_files
output_files
 
 
simulation/activehdl
simulation/activehdl
 
 
ALU.v
ALU.v
 
 
ALU.v.bak
ALU.v.bak
 
 
Control.v
Control.v
 
 
Control.v.bak
Control.v.bak
 
 
DataMemory.v
DataMemory.v
 
 
DataMemory.v.bak
DataMemory.v.bak
 
 
EX_MEM_reg.v
EX_MEM_reg.v
 
 
EX_MEM_reg.v.bak
EX_MEM_reg.v.bak
 
 
ID_EX_reg.v
ID_EX_reg.v
 
 
ID_EX_reg.v.bak
ID_EX_reg.v.bak
 
 
IF_ID_reg.v
IF_ID_reg.v
 
 
IF_ID_reg.v.bak
IF_ID_reg.v.bak
 
 
MEM_WB_reg.v
MEM_WB_reg.v
 
 
MEM_WB_reg.v.bak
MEM_WB_reg.v.bak
 
 
README.md
README.md
 
 
StageFive.v
StageFive.v
 
 
StageFive.v.bak
StageFive.v.bak
 
 
StageFour.v
StageFour.v
 
 
StageFour.v.bak
StageFour.v.bak
 
 
StageOne.v
StageOne.v
 
 
StageOne.v.bak
StageOne.v.bak
 
 
StageThree.v
StageThree.v
 
 
StageThree.v.bak
StageThree.v.bak
 
 
StageTwo.v
StageTwo.v
 
 
StageTwo.v.bak
StageTwo.v.bak
 
 
add_32.v
add_32.v
 
 
add_32.v.bak
add_32.v.bak
 
 
alu_control.v
alu_control.v
 
 
alu_control.v.bak
alu_control.v.bak
 
 
cpu.v
cpu.v
 
 
cpu.v.bak
cpu.v.bak
 
 
instruction_memory.v
instruction_memory.v
 
 
instruction_memory.v.bak
instruction_memory.v.bak
 
 
instructions.txt
instructions.txt
 
 
instructions_beq.txt
instructions_beq.txt
 
 
instructions_mips.txt
instructions_mips.txt
 
 
intsructions_bne.txt
intsructions_bne.txt
 
 
mips_project.qpf
mips_project.qpf
 
 
mips_project.qsf
mips_project.qsf
 
 
mips_project.qws
mips_project.qws
 
 
mips_project.v
mips_project.v
 
 
mips_project.v.bak
mips_project.v.bak
 
 
mips_project_nativelink_simulation.rpt
mips_project_nativelink_simulation.rpt
 
 
mux_2x1_32.v
mux_2x1_32.v
 
 
mux_2x1_32.v.bak
mux_2x1_32.v.bak
 
 
mux_2x1_5.v
mux_2x1_5.v
 
 
mux_2x1_5.v.bak
mux_2x1_5.v.bak
 
 
pc_4.v
pc_4.v
 
 
pc_4.v.bak
pc_4.v.bak
 
 
reg32.v
reg32.v
 
 
reg32.v.bak
reg32.v.bak
 
 
register_file.v
register_file.v
 
 
register_file.v.bak
register_file.v.bak
 
 
shift_left_2.v
shift_left_2.v
 
 
shift_left_2.v.bak
shift_left_2.v.bak
 
 
sign_extender_16to32.v
sign_extender_16to32.v
 
 
sign_extender_16to32.v.bak
sign_extender_16to32.v.bak
 
 
test.v
test.v
 
 
test.v.bak
test.v.bak
 
 
verilog.key
verilog.key
 
 
verilog.log
verilog.log
 
 

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mips-processor

This a 5-staged pipelined mips processor using Verilog done using ModelSim Altera

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This a 5-staged pipelined mips processor using Verilog

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