I can't create my own JK flip flop and counter

[VerdichteteEnergie]

My goal is to build my own chips from logic gates and then use them for other circuits.

Unfortunately I can't build a JK flip flop and a counter.
After trying several versions of circuits I didn't get any success.

Now I want start with the simplest options for a JK flip flop and a counter.

Can anyone help me or link to a schematic wich works for digital? I'm obviously too stupid to find anything suitable on google...

Please don't be surprised, I'm a beginner.

My JK Flip Flop

My Counter

[hneemann]

The idea for your JK flip-flop is not so bad. You just overlooked that your circuit essentially corresponds to an inverter which is fed back to itself:

Such a circuit cannot achieve a stabilized state.

Therefore, this direct feedback must be prevented for the circuit to work.
And there are two ways to do that: One can either make the switching pulse so short that no oscillation can occur, because there is not enough time for that. To do this, the rising edge is transformed into a very short pulse. Just long enough to toggle the flipflop, but not long enough for multiple toggles.

The three gates directly behind the clock input are used to generate the pulse.

The second possibility is to use both edges, the rising and the falling edge of the clock to forward the signal. This approach leads to a master-slave flip-flop. Since the clock cannot be high and low at the same time, the flipflop is never transparent with respect to changes of an input.

Both implementations can be found in the examples folder (examples/sequential/JK-T.dig and JK-MS.dig).

[VerdichteteEnergie]

Thank You very much! From now on I always look at the examples.

[hneemann]

Don't be afraid to keep asking questions here! 😄

[jongena]

Thank you for the interesting discussion. I tried to study the detailed behaviour of the pulses in the two cases given by Mr. Neeman and then to compare with the non working J-K flip flop shown at the very beginning of the discussion. To see all details I used the
"Show measurement graph at the beginning of the simulation in single gate mode" [Clicking "Edit" at the top of the Digital screen, then select in the pop-up window "Circuit specific settings"; then in the new window click "Advanced" and in the new pop-up window click "Show measurement graph at the beginning of the simulation in single gate mode"). This then keeps the results of the graph on the screen when the simulation stops. However, this went fine as long as there were no oscillations. See the graphs attached: the first one obtained when stopping the simulation without oscillations (e.g. in this case J high or low, with K low); the second one when oscillations occurred (when putting both J and K inputs high): all past timing info for the inputs J, K, and clock are erased. The outputs Q and not Q also show suddenly something else than that what was on the screen before the oscillations were present.

Q1: What did I overlook ?
Q2: How to get the right graph (and keep the detailed time history) at the moment the oscillations appear?
Q3: If the answer on Q1 and Q2 is negative now, can this be corrected in a next version of Digital ?

[hneemann]

Perhaps this helps to understand why the top most circuit does not stablize:

Oszillation.mp4

[jongena]

Dear Mr. Neemann, many thanks for the very nice illustration, also again on the use of Digital to analyze in fine detail the sequence of pulses in logic circuits. This indeed clarifies. The clock has to go low before a next Q/non-Q toggle occurs otherwise further Q/non-Q toggles will occur and thus the circuit cannot arrive at a stable state. Excellent example !