Initial value of counter varies

[jnoche]

(I don't know if I should post this as an Issue or as a Discussion.)
I have a circuit with a counter (Instr Counter) that sometimes starts with a 0 and sometimes starts with a 1 (when the simulation is started).


I'm using the latest version of Digital (OS: Windows 10 OS version: 10.0 JRE: 15.0.1 VM: 15.0.1+9-18 Digital.jar Build Git-Revision: v0.30-11-g71c9770 Build Time: 2023-06-14 13:54).

Is there a way to "fix" this so that the counter always starts at 0 at start up?

[hneemann]

In the start-up phase of the circuit, all gates must reach a stable state. This happens in a more or less random way. It can happen that in this start phase the counter receives a clock pulse. To prevent the counter from counting in this situation, the enable input of the counter must be held at zero during the start phase. To achieve this, the 1 at the enable input can be replaced by a reset component.

[jnoche]

I actually tried that, and it still initialized at 1 or at 0 randomly. Even if I place a delay element.

Edit: Oops, the reset component should have an inverted output here.

[jnoche]

Hmm... I tried replacing the fixed 1 at the enable input with a reset (with inverted output) in series with a delay, but now set the delay to 5 gate delays and it seems to work now.
Thank you very much! I think I've found the solution.

[hneemann]

Are there other reset components in the circuit? Then it is possible that switching one of the other reset components triggers a kind of second settling phase, which then clocks the counter.

[jnoche]

If I'm not mistaken, the circuit had no other reset components when I ran the test mentioned in my answer. But now I've edited the circuit to replace instances having the fixed 1 with the reset and delay, so now my circuit has many reset components.

[hneemann]

If all reset components switch on an enable signal, it does not matter how many there are. It becomes problematic, if the switching of a reset component causes output signals to change, because a new cascade of changes can be initiated. But now all reset outputs are switched, and all enable signals are therefore set to "active". This second wave of changes can then, for example, clock counters or similar.
Adding delay components to wait until this second wave of changes has passed doesn't seem like a good solution to me. It would be better to prevent this second wave of changes from occurring.

[jnoche]

I admit that my solution is a bit inelegant. Thanks for the advice.