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em_6502.c
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em_6502.c
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#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <inttypes.h>
#include "memory.h"
#include "tube_decode.h"
#include "em_6502.h"
// ====================================================================
// Type Defs
// ====================================================================
typedef enum {
IMP,
IMPA,
BRA,
IMM,
ZP,
ZPX,
ZPY,
INDX,
INDY,
IND,
ABS,
ABSX,
ABSY,
IND16,
IND1X,
ZPR
} AddrMode ;
typedef enum {
READOP,
WRITEOP,
RMWOP,
BRANCHOP,
OTHER
} OpType;
typedef struct {
int len;
const char *fmt;
} AddrModeType;
typedef int operand_t;
typedef int ea_t;
typedef struct {
const char *mnemonic;
int undocumented;
AddrMode mode;
int cycles;
int decimalcorrect;
OpType optype;
int (*emulate)(operand_t, ea_t);
int len;
const char *fmt;
} InstrType;
// ====================================================================
// Static variables
// ====================================================================
#define OFFSET_A 2
#define OFFSET_X 7
#define OFFSET_Y 12
#define OFFSET_S 18
#define OFFSET_N 23
#define OFFSET_V 27
#define OFFSET_D 31
#define OFFSET_I 35
#define OFFSET_Z 39
#define OFFSET_C 43
#define OFFSET_END 44
static const char default_state[] = "A=?? X=?? Y=?? SP=?? N=? V=? D=? I=? Z=? C=?";
static int rockwell = 0;
static int arlet = 0;
static int aland = 0;
static int c02 = 0;
static int bbctube = 0;
static int master_nordy = 0;
static InstrType *instr_table;
static AddrModeType addr_mode_table[] = {
{1, "%1$s"}, // IMP
{1, "%1$s A"}, // IMPA
{2, "%1$s %2$s"}, // BRA
{2, "%1$s #%2$02X"}, // IMM
{2, "%1$s %2$02X"}, // ZP
{2, "%1$s %2$02X,X"}, // ZPX
{2, "%1$s %2$02X,Y"}, // ZPY
{2, "%1$s (%2$02X,X)"}, // INDX
{2, "%1$s (%2$02X),Y"}, // INDY
{2, "%1$s (%2$02X)"}, // IND
{3, "%1$s %3$02X%2$02X"}, // ABS
{3, "%1$s %3$02X%2$02X,X"}, // ABSX
{3, "%1$s %3$02X%2$02X,Y"}, // ABSY
{3, "%1$s (%3$02X%2$02X)"}, // IND1
{3, "%1$s (%3$02X%2$02X,X)"}, // IND1X
{3, "%1$s %2$02X,%3$s"} // ZPR
};
// 6502 registers: -1 means unknown
static int A = -1;
static int X = -1;
static int Y = -1;
static int S = -1;
static int PC = -1;
// 6502 flags: -1 means unknown
static int N = -1;
static int V = -1;
static int D = -1;
static int I = -1;
static int Z = -1;
static int C = -1;
static char ILLEGAL[] = "???";
// JSR cycle positions
// <opcode> <op1> <read dummy> <write pch> <write pcl> <op2>
static int jsr_pch = 3;
static int jsr_pcl = 4;
// ====================================================================
// Forward declarations
// ====================================================================
static InstrType instr_table_6502[];
static InstrType instr_table_65c02[];
static int op_STA(operand_t operand, ea_t ea);
static int op_STX(operand_t operand, ea_t ea);
static int op_STY(operand_t operand, ea_t ea);
// ====================================================================
// Helper Methods
// ====================================================================
static int compare_FLAGS(int operand) {
if (N >= 0) {
if (N != ((operand >> 7) & 1)) {
return 1;
}
}
if (V >= 0) {
if (V != ((operand >> 6) & 1)) {
return 1;
}
}
if (D >= 0) {
if (D != ((operand >> 3) & 1)) {
return 1;
}
}
if (I >= 0) {
if (I != ((operand >> 2) & 1)) {
return 1;
}
}
if (Z >= 0) {
if (Z != ((operand >> 1) & 1)) {
return 1;
}
}
if (C >= 0) {
if (C != ((operand >> 0) & 1)) {
return 1;
}
}
return 0;
}
static void check_FLAGS(int operand) {
failflag |= compare_FLAGS(operand);
}
static void set_FLAGS(int operand) {
N = (operand >> 7) & 1;
V = (operand >> 6) & 1;
D = (operand >> 3) & 1;
I = (operand >> 2) & 1;
Z = (operand >> 1) & 1;
C = (operand >> 0) & 1;
}
static void set_NZ_unknown() {
N = -1;
Z = -1;
}
static void set_NZC_unknown() {
N = -1;
Z = -1;
C = -1;
}
static void set_NVZC_unknown() {
N = -1;
V = -1;
Z = -1;
C = -1;
}
static void set_NZ(int value) {
N = (value & 128) > 0;
Z = value == 0;
}
static void pop8(int value) {
if (S >= 0) {
S = (S + 1) & 0xff;
memory_read(value & 0xff, 0x100 + S, MEM_STACK);
}
}
static void push8(int value) {
if (S >= 0) {
memory_write(value & 0xff, 0x100 + S, MEM_STACK);
S = (S - 1) & 0xff;
}
}
static void push16(int value) {
push8(value >> 8);
push8(value);
}
static void interrupt(sample_t *sample_q, int num_cycles, instruction_t *instruction, int pc_offset) {
// Parse the bus cycles
// <opcode> <op1> <write pch> <write pcl> <write p> <read rst> <read rsth>
int pc = (sample_q[2].data << 8) + sample_q[3].data;
int flags = sample_q[4].data;
int vector = (sample_q[6].data << 8) + sample_q[5].data;
// Update the address of the interruted instruction
instruction->pc = (pc - pc_offset) & 0xffff;
// Stack the PB/PC/FLags (for memory modelling)
push16(pc);
push8(flags);
// Validate the flags
check_FLAGS(flags);
// And make them consistent
set_FLAGS(flags);
// Setup expected state for the ISR
I = 1;
if (c02) {
D = 0;
}
PC = vector;
}
static int get_num_cycles(sample_t *sample_q, int intr_seen) {
static int mhz1_phase = 1;
if (intr_seen) {
mhz1_phase ^= 1;
return 7;
}
int opcode = sample_q[0].data;
int op1 = sample_q[1].data;
int op2 = sample_q[opcode == 0x20 ? 5 : ((opcode & 0x0f) == 0x0f) ? 4 : 2].data;
InstrType *instr = &instr_table[opcode];
int cycle_count = instr->cycles;
// Account for extra cycle in ADC/SBC in decimal mode in C02
if (c02 && instr->decimalcorrect && D == 1) {
cycle_count++;
}
// Account for extra cycle in a page crossing in (indirect), Y (not stores)
// <opcpde> <op1> <addrlo> <addrhi> [ <page crossing>] <<operand> [ <extra cycle in dec mode> ]
if ((instr->mode == INDY) && (instr->optype != WRITEOP) && Y >= 0) {
int base = (sample_q[3].data << 8) + sample_q[2].data;
if ((base & 0xff00) != ((base + Y) & 0xff00)) {
cycle_count++;
}
}
// Account for extra cycle in a page crossing in absolute indexed (not stores)
if ((((instr->mode == ABSX) || (instr->mode == ABSY)) && (instr->optype != WRITEOP)) || (arlet && instr->mode == IND1X)) {
// 6502: Need to exclude ASL/ROL/LSR/ROR/DEC/INC, which are 7 cycles regardless
// 65C02: Need to exclude DEC/INC, which are 7 cycles regardless
if ((opcode != 0xDE) && (opcode != 0xFE) && ((c02 && !arlet && !aland) || ((opcode != 0x1E) && (opcode != 0x3E) && (opcode != 0x5E) && (opcode != 0x7E)))) {
int index = (instr->mode == ABSY) ? Y : X;
if (index >= 0) {
int base = op1 + (op2 << 8);
if ((base & 0xff00) != ((base + index) & 0xff00)) {
cycle_count++;
}
}
}
}
// Account for extra cycles in BBR/BBS
//
// Example: BBR0, $50, +6
// 0 8f 1 1 1 <opcode>
// 1 50 1 0 1 <op1> i.e. ZP address
// 2 01 1 0 1 <mem rd>
// 3 01 1 0 1 <mem rd>
// 4 06 1 0 1 <op2> i.e.
// 5 20 1 0 1 (<branch taken penalty>)
// 6 (<page crossed penalty>)
//
if (rockwell && (opcode & 0x0f) == 0x0f) {
int operand = sample_q[2].data;
// invert operand for BBR
if (opcode <= 0x80) {
operand ^= 0xff;
}
int bit = (opcode >> 4) & 7;
// Figure out if the branch was taken
if (operand & (1 << bit)) {
// A taken bbr/bbs branch is 6 cycles, not 5
cycle_count = 6;
// A taken bbr/bbs branch that crosses a page boundary is 7 cycles
if (PC >= 0) {
int target = (PC + 3) + ((int8_t)(op2));
if ((target & 0xFF00) != ((PC + 3) & 0xff00)) {
cycle_count = 7;
}
}
}
}
// Account for extra cycles in a branch
if (((opcode & 0x1f) == 0x10) || (opcode == 0x80)) {
// Default to backards branches taken, forward not taken
int taken = ((int8_t)op1) < 0;
switch (opcode) {
case 0x10: // BPL
if (N >= 0) {
taken = !N;
}
break;
case 0x30: // BMI
if (N >= 0) {
taken = N;
}
break;
case 0x50: // BVC
if (V >= 0) {
taken = !V;
}
break;
case 0x70: // BVS
if (V >= 0) {
taken = V;
}
break;
case 0x80: // BRA
taken = 1;
break;
case 0x90: // BCC
if (C >= 0) {
taken = !C;
}
break;
case 0xB0: // BCS
if (C >= 0) {
taken = C;
}
break;
case 0xD0: // BNE
if (Z >= 0) {
taken = !Z;
}
break;
case 0xF0: // BEQ
if (Z >= 0) {
taken = Z;
}
break;
}
if (taken) {
// A taken branch is 3 cycles, not 2
cycle_count = 3;
// A taken branch that crosses a page boundary is 4 cycle
if (PC >= 0) {
int target = (PC + 2) + ((int8_t)(op1));
if ((target & 0xFF00) != ((PC + 2) & 0xff00)) {
cycle_count = 4;
}
}
}
}
// Master specific behaviour to remain in sync if rdy is not available
if (master_nordy) {
if (instr->len == 3) {
if ((op2 == 0xfc) || // &FC00-&FCFF
(op2 == 0xfd) || // &FD00-&FDFF
(op2 == 0xfe && (
((op1 & 0xE0) == 0x00) || // &FE00-&FE1F
((op1 & 0xC0) == 0x40) || // &FE40-&FE7F
((op1 & 0xE0) == 0x80) || // &FE80-&FE9F
((op1 & 0xE0) == 0xC0) // &FEC0-&FEDF
))) {
// Use STA/STX/STA to determine 1MHz clock phase
if (opcode == 0x8C || opcode == 0x8D || opcode == 0x8E) {
if (sample_q[3].data == sample_q[4].data) {
int new_phase;
if (sample_q[3].data == sample_q[5].data) {
new_phase = 1;
} else {
new_phase = 0;
}
if (mhz1_phase != new_phase) {
//printf("correcting 1MHz phase\n");
mhz1_phase = new_phase;
}
} else {
printf("fail: 1MHz access not extended as expected\n");
}
}
// Correct cycle count based on expected cycle stretching behaviour
if (opcode == 0x9D) {
// STA abs, X which has an unfortunate dummy cycle
cycle_count += 2 + mhz1_phase;
} else {
cycle_count += 1 + mhz1_phase;
}
}
}
// Toggle the phase every cycle
mhz1_phase ^= (cycle_count & 1);
}
return cycle_count;
}
static int count_cycles_without_sync(sample_t *sample_q, int intr_seen) {
int num_cycles = get_num_cycles(sample_q, intr_seen);
if (num_cycles >= 0) {
return num_cycles;
}
printf ("cycle prediction unknown\n");
return 1;
}
static int count_cycles_with_sync(sample_t *sample_q, int intr_seen) {
if (sample_q[0].type == OPCODE) {
for (int i = 1; i < DEPTH; i++) {
if (sample_q[i].type == LAST) {
return 0;
}
if (sample_q[i].type == OPCODE) {
// Validate the num_cycles passed in
int expected = get_num_cycles(sample_q, intr_seen);
if (expected >= 0) {
if (i != expected) {
printf ("opcode %02x: cycle prediction fail: expected %d actual %d\n", sample_q[0].data, expected, i);
}
}
return i;
}
}
}
return 1;
}
// ====================================================================
// Public Methods
// ====================================================================
static void em_6502_init(arguments_t *args) {
switch (args->cpu_type) {
case CPU_6502:
instr_table = instr_table_6502;
break;
case CPU_6502_ARLET:
arlet = 1;
jsr_pch = 2;
jsr_pcl = 3;
instr_table = instr_table_6502;
break;
case CPU_65C02_ROCKWELL:
rockwell = 1;
c02 = 1;
instr_table = instr_table_65c02;
break;
case CPU_65C02_ARLET:
arlet = 1;
c02 = 1;
jsr_pch = 2;
jsr_pcl = 3;
instr_table = instr_table_65c02;
break;
case CPU_65C02_ALAND:
aland = 1;
c02 = 1;
instr_table = instr_table_65c02;
break;
case CPU_65C02:
c02 = 1;
instr_table = instr_table_65c02;
break;
default:
printf("em_6502_init called with unsupported cpu_type (%d)\n", args->cpu_type);
exit(1);
}
bbctube = args->bbctube;
// Initialize the SP
if (args->sp_reg >= 0) {
S = args->sp_reg & 0xff;
}
// This flag tells the sync-less cycle count estimation to infer additional cycles on the master
// It's needed when rdy is not being explicitely sampled
master_nordy = (args->machine == MACHINE_MASTER) && (args->idx_rdy < 0);
if (args->cpu_type == CPU_65C02_ARLET) {
// Arlet's 65C02 is really an NMOS 6502 with extra instructions
// The NMOS instructions have NMOS cycle counts
instr_table[0x6c].cycles = 5; // JMP (ind)
instr_table[0x7c].cycles = 5; // JMP (ind, X)
instr_table[0x1e].cycles = 7; // ASL absx
instr_table[0x3e].cycles = 7; // ROL absx
instr_table[0x5e].cycles = 7; // LSR absx
instr_table[0x7e].cycles = 7; // ROR absx
// CMOS instructions
instr_table[0x5c].cycles = 4; // NOP (should take 8 cycles)
for (int i = 0x00; i <= 0xf0; i+= 0x10) {
instr_table[i + 0x03].cycles = 2; // NOP (should take 1 cycle)
instr_table[i + 0x0B].cycles = 2; // NOP (should take 1 cycle)
}
for (int i = 0x00; i <= 0xff; i++) {
instr_table[i].decimalcorrect = 0; // Not cycle penalty for decimal correct
if (instr_table[i].mode == IND) {
instr_table[i].cycles = 6; // indirect addressing should take 5 cycles
}
}
}
if (args->cpu_type == CPU_65C02_ALAND) {
// Alan D's 65C02 is mostly cycle accurate, with a few exceptions
instr_table[0x40].cycles = 7; // RTI
instr_table[0x1e].cycles = 7; // ASL absx
instr_table[0x3e].cycles = 7; // ROL absx
instr_table[0x5e].cycles = 7; // LSR absx
instr_table[0x7e].cycles = 7; // ROR absx
instr_table[0x44].cycles = 2; // NOP (should take 3 cycles)
instr_table[0x54].cycles = 2; // NOP (should take 4 cycles)
instr_table[0x5c].cycles = 4; // NOP (should take 8 cycles)
instr_table[0xd4].cycles = 2; // NOP (should take 4 cycles)
instr_table[0xf4].cycles = 2; // NOP (should take 4 cycles)
for (int i = 0x00; i <= 0xff; i++) {
instr_table[i].decimalcorrect = 0; // Not cycle penalty for decimal correct
}
}
// If not supporting the Rockwell C02 extensions, tweak the cycle countes
if (args->cpu_type == CPU_65C02 || args->cpu_type == CPU_65C02_ARLET || args->cpu_type == CPU_65C02_ALAND) {
// x7 (RMB/SMB): 5 cycles -> 1 cycles (2 on Arlet's core)
// xF (BBR/BBS): 5 cycles -> 1 cycles (2 on Arlet's core)
int cycles = args->cpu_type == CPU_65C02_ARLET ? 2 : 1;
for (int i = 0x07; i <= 0xff; i+= 0x08) {
instr_table[i].mnemonic = ILLEGAL;
instr_table[i].mode = IMP;
instr_table[i].cycles = cycles;
instr_table[i].optype = READOP;
instr_table[i].len = 1;
}
}
InstrType *instr = instr_table;
for (int i = 0; i < 256; i++) {
// Remove the undocumented instructions, if not supported
if (instr->undocumented && !args->undocumented) {
instr->mnemonic = ILLEGAL;
instr->mode = IMP;
instr->cycles = 1;
}
// Copy the length and format from the address mode, for efficiency
instr->len = addr_mode_table[instr->mode].len;
instr->fmt = addr_mode_table[instr->mode].fmt;
instr++;
}
}
static int em_6502_match_interrupt(sample_t *sample_q, int num_samples) {
// Check we have enough valid samples
if (num_samples < 7) {
return 0;
}
// An interupt will write PCH, PCL, PSW in bus cycles 2,3,4
if (sample_q[0].rnw >= 0) {
// If we have the RNW pin connected, then just look for these three writes in succession
// Currently can't detect a BRK being interrupted
if (sample_q[0].data == 0x00) {
return 0;
}
if (sample_q[2].rnw == 0 && sample_q[3].rnw == 0 && sample_q[4].rnw == 0) {
return 1;
}
} else {
// If not, then we use a heuristic, based on what we expect to see on the data
// bus in cycles 2, 3 and 4, i.e. PCH, PCL, PSW
if (sample_q[2].data == ((PC >> 8) & 0xff) && sample_q[3].data == (PC & 0xff)) {
// Now test unused flag is 1, B is 0
if ((sample_q[4].data & 0x30) == 0x20) {
// Finally test all other known flags match
if (!compare_FLAGS(sample_q[4].data)) {
// Matched PSW = NV-BDIZC
return 1;
}
}
}
}
return 0;
}
static int em_6502_count_cycles(sample_t *sample_q, int intr_seen) {
if (sample_q[0].type == UNKNOWN) {
return count_cycles_without_sync(sample_q, intr_seen);
} else {
return count_cycles_with_sync(sample_q, intr_seen);
}
}
static void em_6502_reset(sample_t *sample_q, int num_cycles, instruction_t *instruction) {
instruction->pc = -1;
A = -1;
X = -1;
Y = -1;
S = -1;
N = -1;
V = -1;
D = -1;
Z = -1;
C = -1;
I = 1;
if (c02) {
D = 0;
}
PC = (sample_q[num_cycles - 1].data << 8) + sample_q[num_cycles - 2].data;
}
static void em_6502_interrupt(sample_t *sample_q, int num_cycles, instruction_t *instruction) {
interrupt(sample_q, num_cycles, instruction, 0);
}
static void em_6502_emulate(sample_t *sample_q, int num_cycles, instruction_t *instruction) {
// Unpack the instruction bytes
int opcode = sample_q[0].data;
// lookup the entry for the instruction
InstrType *instr = &instr_table[opcode];
int opcount = instr->len - 1;
int op1 = (opcount < 1) ? 0 : sample_q[1].data;
int op2 =
(opcount < 2) ? 0 :
(opcode == 0x20) ? sample_q[5].data :
((opcode & 0x0f) == 0x0f) ? sample_q[4].data : sample_q[2].data;
// Memory Modelling: Instruction fetches
if (PC >= 0) {
int pc = PC;
memory_read(opcode, pc++, MEM_FETCH);
if (opcount >= 1) {
memory_read(op1, pc++, MEM_INSTR);
}
if (opcount >= 2) {
memory_read(op2, pc++, MEM_INSTR);
}
}
// Save the instruction state
instruction->opcode = opcode;
instruction->op1 = op1;
instruction->op2 = op2;
instruction->opcount = opcount;
// Determine the current PC value
if (opcode == 0x00) {
// Now just pass BRK onto the interrupt handler
interrupt(sample_q, num_cycles, instruction, 2);
// And we are done
return;
} else if (opcode == 0x20) {
instruction->pc = (((sample_q[jsr_pch].data << 8) + sample_q[jsr_pcl].data) - 2) & 0xffff;
} else {
instruction->pc = PC;
}
// Memory Modelling: Pointer indirection
switch (instr->mode) {
case IND:
// C02: <opcode> <op1> <addrlo> <addrhi> <operand>
// Arlet C02: <opcode> <op1> <addrlo> <addrlo> <addrhi> <operand>
memory_read(sample_q[arlet ? 3 : 2].data, op1 , MEM_POINTER);
memory_read(sample_q[arlet ? 4 : 3].data, ((op1 + 1) & 0xff), MEM_POINTER);
break;
case INDY:
// <opcode> <op1> <addrlo> <addrhi> [ <page crossing>] <operand>
memory_read(sample_q[2].data, op1 , MEM_POINTER);
memory_read(sample_q[3].data, ((op1 + 1) & 0xff), MEM_POINTER);
break;
case INDX:
// <opcode> <op1> <dummy> <addrlo> <addrhi> <operand>
if (X >= 0) {
memory_read(sample_q[3].data, ((op1 + X ) & 0xff), MEM_POINTER);
memory_read(sample_q[4].data, ((op1 + X + 1) & 0xff), MEM_POINTER);
}
break;
case IND16:
// e.g. JMP (1234)
// <opcode=6C> <op1> <op2> <read new pcl> <read new pch>
if (c02) {
memory_read(sample_q[num_cycles - 2].data, (op2 << 8) + op1 , MEM_POINTER);
memory_read(sample_q[num_cycles - 1].data, ((op2 << 8) + op1 + 1) & 0xffff, MEM_POINTER);
} else {
memory_read(sample_q[num_cycles - 2].data, (op2 << 8) + op1 , MEM_POINTER);
memory_read(sample_q[num_cycles - 1].data, (op2 << 8) + ((op1 + 1) & 0xff), MEM_POINTER);
}
break;
case IND1X:
// JMP: <opcode=7C> <op1> <op2> <dummy> <read new pcl> <read new pch>
if (X >= 0) {
memory_read(sample_q[num_cycles - 2].data, ((op2 << 8) + op1 + X ) & 0xffff, MEM_POINTER);
memory_read(sample_q[num_cycles - 1].data, ((op2 << 8) + op1 + X + 1) & 0xffff, MEM_POINTER);
}
break;
default:
break;
}
if (instr->emulate) {
int operand;
if (instr->optype == RMWOP) {
// e.g. <opcode> <op1> <op2> <read old> <write old> <write new>
// <opcode> <op1> <read old> <write old> <write new>
// Want to pick off the read
operand = sample_q[num_cycles - 3].data;
} else if (instr->optype == BRANCHOP) {
// the operand is true if branch taken
operand = (num_cycles != 2);
} else if (opcode == 0x00) {
// BRK: the operand is the data pushed to the stack (PCH, PCL, P)
// <opcode> <op1> <write pch> <write pcl> <write p> <read rst> <read rsth>
operand = (sample_q[2].data << 16) + (sample_q[3].data << 8) + sample_q[4].data;
} else if (opcode == 0x20) {
// JSR: the operand is the data pushed to the stack (PCH, PCL)
// <opcode> <op1> <read dummy> <write pch> <write pcl> <op2>
operand = (sample_q[jsr_pch].data << 8) + sample_q[jsr_pcl].data;
} else if (opcode == 0x40) {
// RTI: the operand is the data pulled from the stack (P, PCL, PCH)
// C02: <opcode> <op1> <read dummy> <read p> <read pcl> <read pch>
// AlanDC02: <opcode> <op1> <read dummy> <read p> <read pcl> <read pcl> <read pch>
operand = (sample_q[num_cycles - 1].data << 16) + (sample_q[num_cycles - 2].data << 8) + sample_q[3].data;
} else if (opcode == 0x60) {
// RTS: the operand is the data pulled from the stack (PCL, PCH)
// <opcode> <op1> <read dummy> <read pcl> <read pch>
operand = (sample_q[4].data << 8) + sample_q[3].data;
} else if (instr->mode == IMM) {
// Immediate addressing mode: the operand is the 2nd byte of the instruction
operand = op1;
} else if (instr->decimalcorrect && (D == 1)) {
// read operations on the C02 that have an extra cycle added
operand = sample_q[num_cycles - 2].data;
} else {
// default to using the last bus cycle as the operand
operand = sample_q[num_cycles - 1].data;
}
// Operand 2 is the value written back in a store or read-modify-write
// See RMW comment above for bus cycles
operand_t operand2 = operand;
if (instr->optype == RMWOP || instr->optype == WRITEOP) {
operand2 = sample_q[num_cycles - 1].data;
}
// For instructions that read or write memory, we need to work out the effective address
// Note: not needed for stack operations, as S is used directly
int ea = -1;
int index;
switch (instr->mode) {
case ZP:
case ZPR:
ea = op1;
break;
case ZPX:
case ZPY:
index = instr->mode == ZPX ? X : Y;
if (index >= 0) {
ea = (op1 + index) & 0xff;
}
break;
case INDY:
// <opcpde> <op1> <addrlo> <addrhi> [ <page crossing>] <<operand> [ <extra cycle in dec mode> ]
index = Y;
if (index >= 0) {
ea = (sample_q[3].data << 8) + sample_q[2].data;
ea = (ea + index) & 0xffff;
}
break;
case INDX:
// <opcpde> <op1> <dummy> <addrlo> <addrhi> <operand> [ <extra cycle in dec mode> ]
ea = (sample_q[4].data << 8) + sample_q[3].data;
break;
case IND:
// <opcpde> <op1> <addrlo> <addrhi> <operand> [ <extra cycle in dec mode> ]
ea = (sample_q[arlet ? 4 : 3].data << 8) + sample_q[arlet ? 3 : 2].data;
break;
case ABS:
ea = op2 << 8 | op1;
break;
case ABSX:
case ABSY:
index = instr->mode == ABSX ? X : Y;
if (index >= 0) {
ea = ((op2 << 8 | op1) + index) & 0xffff;
}
break;
default:
// covers IMM, IMP, IMPA, IND16, IND1X, BRA
break;
}
// Model memory reads
if (ea >= 0 && (instr->optype == READOP || instr->optype == RMWOP)) {
memory_read(operand, ea, MEM_DATA);
}
// Execute the instruction specific function
// (This returns -1 if the result is unknown or invalid)
int result = instr->emulate(operand, ea);
if (instr->optype == WRITEOP || instr->optype == RMWOP) {
// STA STX STY STZ
// INC DEX ASL LSR ROL ROR
// TSB TRB RMB SMB
// Check result of instruction against bye
if (result >= 0 && result != operand2) {
failflag |= 1;
}
// Model memory writes based on result seen on bus
if (ea >= 0) {
memory_write(operand2, ea, MEM_DATA);
}
}
}
// Look for control flow changes and update the PC
if (opcode == 0x40 || opcode == 0x6c || opcode == 0x7c) {
// RTI, JMP (ind), JMP (ind, X)
PC = (sample_q[num_cycles - 1].data << 8) | sample_q[num_cycles - 2].data;
} else if (opcode == 0x20 || opcode == 0x4c) {
// JSR abs, JMP abs
PC = op2 << 8 | op1;
} else if (PC < 0) {
// PC value is not known yet, everything below this point is relative
PC = -1;
} else if (opcode == 0x80) {
// BRA
PC = (PC + ((int8_t)(op1)) + 2) & 0xffff;
} else if (rockwell && ((opcode & 0x0f) == 0x0f) && (num_cycles != 5)) {
// BBR/BBS: op2 if taken
PC = (PC + ((int8_t)(op2)) + 3) & 0xffff;
} else if ((opcode & 0x1f) == 0x10 && num_cycles != 2) {
// BXX: op1 if taken
PC = (PC + ((int8_t)(op1)) + 2) & 0xffff;
} else {
// Otherwise, increment pc by length of instuction
PC = (PC + opcount + 1) & 0xffff;
}
}
static int em_6502_disassemble(char *buffer, instruction_t *instruction) {
int numchars;
int offset;
char target[16];
// Unpack the instruction bytes
int opcode = instruction->opcode;
int op1 = instruction->op1;
int op2 = instruction->op2;
int pc = instruction->pc;
// lookup the entry for the instruction
InstrType *instr = &instr_table[opcode];
const char *mnemonic = instr->mnemonic;
const char *fmt = instr->fmt;
switch (instr->mode) {
case IMP:
case IMPA:
numchars = sprintf(buffer, fmt, mnemonic);
break;
case BRA:
// Calculate branch target using op1 for normal branches
offset = (int8_t) op1;
if (pc < 0) {
if (offset < 0) {
sprintf(target, "pc-%d", -offset);
} else {
sprintf(target,"pc+%d", offset);
}
} else {
sprintf(target, "%04X", (pc + 2 + offset) & 0xffff);
}
numchars = sprintf(buffer, fmt, mnemonic, target);
break;
case ZPR:
// Calculate branch target using op2 for BBR/BBS
offset = (int8_t) op2;
if (pc < 0) {
if (offset < 0) {
sprintf(target, "pc-%d", -offset);
} else {
sprintf(target,"pc+%d", offset);
}
} else {
sprintf(target, "%04X", (pc + 3 + offset) & 0xffff);
}
numchars = sprintf(buffer, fmt, mnemonic, op1, target);
break;
case IMM:
case ZP:
case ZPX:
case ZPY:
case INDX:
case INDY:
case IND:
numchars = sprintf(buffer, fmt, mnemonic, op1);
break;
case ABS:
case ABSX:
case ABSY:
case IND16:
case IND1X:
numchars = sprintf(buffer, fmt, mnemonic, op1, op2);
break;
default:
numchars = 0;
}
return numchars;
}
static int em_6502_get_PC() {
return PC;
}
static int em_6502_get_PB() {
return 0;
}
static int em_6502_read_memory(int address) {
return memory_read_raw(address);
}
static char *em_6502_get_state(char *buffer) {
strcpy(buffer, default_state);
if (A >= 0) {
write_hex2(buffer + OFFSET_A, A);
}
if (X >= 0) {
write_hex2(buffer + OFFSET_X, X);
}
if (Y >= 0) {
write_hex2(buffer + OFFSET_Y, Y);
}
if (S >= 0) {
write_hex2(buffer + OFFSET_S, S);
}
if (N >= 0) {
buffer[OFFSET_N] = '0' + N;
}
if (V >= 0) {
buffer[OFFSET_V] = '0' + V;
}
if (D >= 0) {
buffer[OFFSET_D] = '0' + D;
}
if (I >= 0) {
buffer[OFFSET_I] = '0' + I;
}