/
ArmEmitter.cpp
3209 lines (2834 loc) · 109 KB
/
ArmEmitter.cpp
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// Copyright (C) 2003 Dolphin Project.
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, version 2.0.
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License 2.0 for more details.
// A copy of the GPL 2.0 should have been included with the program.
// If not, see http://www.gnu.org/licenses/
// Official SVN repository and contact information can be found at
// http://code.google.com/p/dolphin-emu/
#include "base/logging.h"
#include <assert.h>
#include <stdarg.h>
#include <stddef.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#ifdef IOS
#include <libkern/OSCacheControl.h>
#include <sys/mman.h>
#endif
#include "MemoryUtil.h"
#include "ArmEmitter.h"
#include "CPUDetect.h"
// Want it in release builds too
#ifdef ANDROID
#undef _dbg_assert_msg_
#define _dbg_assert_msg_ _assert_msg_
#endif
namespace ArmGen
{
inline u32 RotR(u32 a, int amount) {
if (!amount) return a;
return (a >> amount) | (a << (32 - amount));
}
inline u32 RotL(u32 a, int amount) {
if (!amount) return a;
return (a << amount) | (a >> (32 - amount));
}
bool TryMakeOperand2(u32 imm, Operand2 &op2) {
// Just brute force it.
for (int i = 0; i < 16; i++) {
int mask = RotR(0xFF, i * 2);
if ((imm & mask) == imm) {
op2 = Operand2((u8)(RotL(imm, i * 2)), (u8)i);
return true;
}
}
return false;
}
bool TryMakeOperand2_AllowInverse(u32 imm, Operand2 &op2, bool *inverse)
{
if (!TryMakeOperand2(imm, op2)) {
*inverse = true;
return TryMakeOperand2(~imm, op2);
} else {
*inverse = false;
return true;
}
}
bool TryMakeOperand2_AllowNegation(s32 imm, Operand2 &op2, bool *negated)
{
if (!TryMakeOperand2(imm, op2)) {
*negated = true;
return TryMakeOperand2(-imm, op2);
} else {
*negated = false;
return true;
}
}
Operand2 AssumeMakeOperand2(u32 imm) {
Operand2 op2;
bool result = TryMakeOperand2(imm, op2);
_dbg_assert_msg_(JIT, result, "Could not make assumed Operand2.");
if (!result) {
// Make double sure that we get it logged.
ERROR_LOG(JIT, "Could not make assumed Operand2.");
}
return op2;
}
bool ARMXEmitter::TrySetValue_TwoOp(ARMReg reg, u32 val)
{
int ops = 0;
for (int i = 0; i < 16; i++)
{
if ((val >> (i*2)) & 0x3)
{
ops++;
i+=3;
}
}
if (ops > 2)
return false;
bool first = true;
for (int i = 0; i < 16; i++, val >>=2) {
if (val & 0x3) {
first ? MOV(reg, Operand2((u8)val, (u8)((16-i) & 0xF)))
: ORR(reg, reg, Operand2((u8)val, (u8)((16-i) & 0xF)));
first = false;
i+=3;
val >>= 6;
}
}
return true;
}
bool TryMakeFloatIMM8(u32 val, Operand2 &op2)
{
if ((val & 0x0007FFFF) == 0)
{
// VFP Encoding for Imms: <7> Not(<6>) Repeat(<6>,5) <5:0> Zeros(19)
bool bit6 = (val & 0x40000000) == 0x40000000;
bool canEncode = true;
for (u32 mask = 0x20000000; mask >= 0x02000000; mask >>= 1)
{
if (((val & mask) == mask) == bit6)
canEncode = false;
}
if (canEncode)
{
u32 imm8 = (val & 0x80000000) >> 24; // sign bit
imm8 |= (!bit6 << 6);
imm8 |= (val & 0x01F80000) >> 19;
op2 = IMM(imm8);
return true;
}
}
return false;
}
void ARMXEmitter::MOVI2FR(ARMReg dest, float val, bool negate)
{
union {float f; u32 u;} conv;
conv.f = negate ? -val : val;
MOVI2R(dest, conv.u);
}
void ARMXEmitter::MOVI2F(ARMReg dest, float val, ARMReg tempReg, bool negate)
{
union {float f; u32 u;} conv;
conv.f = negate ? -val : val;
// Try moving directly first if mantisse is empty
Operand2 op2;
if (cpu_info.bVFPv3 && TryMakeFloatIMM8(conv.u, op2))
VMOV(dest, op2);
else
{
MOVI2R(tempReg, conv.u);
VMOV(dest, tempReg);
}
// Otherwise, possible to use a literal pool and VLDR directly (+- 1020)
}
void ARMXEmitter::MOVI2F_neon(ARMReg dest, float val, ARMReg tempReg, bool negate)
{
union {float f; u32 u;} conv;
conv.f = negate ? -val : val;
// Try moving directly first if mantisse is empty
Operand2 op2;
if (cpu_info.bVFPv3 && TryMakeFloatIMM8(conv.u, op2))
VMOV_neon(F_32, dest, conv.u);
else
{
MOVI2R(tempReg, conv.u);
VDUP(F_32, dest, tempReg);
}
// Otherwise, possible to use a literal pool and VLD1 directly (+- 1020)
}
void ARMXEmitter::ADDI2R(ARMReg rd, ARMReg rs, u32 val, ARMReg scratch)
{
if (!TryADDI2R(rd, rs, val)) {
MOVI2R(scratch, val);
ADD(rd, rs, scratch);
}
}
bool ARMXEmitter::TryADDI2R(ARMReg rd, ARMReg rs, u32 val)
{
if (val == 0) {
if (rd != rs)
MOV(rd, rs);
return true;
}
Operand2 op2;
bool negated;
if (TryMakeOperand2_AllowNegation(val, op2, &negated)) {
if (!negated)
ADD(rd, rs, op2);
else
SUB(rd, rs, op2);
return true;
} else {
// Try 16-bit additions and subtractions - easy to test for.
// Should also try other rotations...
if ((val & 0xFFFF0000) == 0) {
// Decompose into two additions.
ADD(rd, rs, Operand2((u8)(val >> 8), 12)); // rotation right by 12*2 == rotation left by 8
ADD(rd, rd, Operand2((u8)(val), 0));
return true;
} else if ((((u32)-(s32)val) & 0xFFFF0000) == 0) {
val = (u32)-(s32)val;
SUB(rd, rs, Operand2((u8)(val >> 8), 12));
SUB(rd, rd, Operand2((u8)(val), 0));
return true;
} else {
return false;
}
}
}
void ARMXEmitter::SUBI2R(ARMReg rd, ARMReg rs, u32 val, ARMReg scratch)
{
if (!TrySUBI2R(rd, rs, val)) {
MOVI2R(scratch, val);
SUB(rd, rs, scratch);
}
}
bool ARMXEmitter::TrySUBI2R(ARMReg rd, ARMReg rs, u32 val)
{
// Just add a negative.
return TryADDI2R(rd, rs, (u32)-(s32)val);
}
void ARMXEmitter::ANDI2R(ARMReg rd, ARMReg rs, u32 val, ARMReg scratch)
{
if (!TryANDI2R(rd, rs, val)) {
MOVI2R(scratch, val);
AND(rd, rs, scratch);
}
}
bool ARMXEmitter::TryANDI2R(ARMReg rd, ARMReg rs, u32 val)
{
Operand2 op2;
bool inverse;
if (val == 0) {
// Avoid the ALU, may improve pipeline.
MOV(rd, 0);
return true;
} else if (TryMakeOperand2_AllowInverse(val, op2, &inverse)) {
if (!inverse) {
AND(rd, rs, op2);
} else {
BIC(rd, rs, op2);
}
return true;
} else {
#ifdef HAVE_ARMV7
// Check if we have a single pattern of sequential bits.
int seq = -1;
for (int i = 0; i < 32; ++i) {
if (((val >> i) & 1) == 0) {
if (seq == -1) {
// The width is all bits previous to this, set to 1.
seq = i;
}
} else if (seq != -1) {
// Uh oh, more than one sequence.
seq = -2;
}
}
if (seq > 0) {
UBFX(rd, rs, 0, seq);
return true;
}
#endif
int ops = 0;
for (int i = 0; i < 32; i += 2) {
u8 bits = RotR(val, i) & 0xFF;
// If either low bit is not set, we need to use a BIC for them.
if ((bits & 3) != 3) {
++ops;
i += 8 - 2;
}
}
// The worst case is 4 (e.g. 0x55555555.)
#ifdef HAVE_ARMV7
if (ops > 3) {
return false;
}
#endif
bool first = true;
for (int i = 0; i < 32; i += 2) {
u8 bits = RotR(val, i) & 0xFF;
if ((bits & 3) != 3) {
u8 rotation = i == 0 ? 0 : 16 - i / 2;
if (first) {
BIC(rd, rs, Operand2(~bits, rotation));
first = false;
} else {
BIC(rd, rd, Operand2(~bits, rotation));
}
// Well, we took care of these other bits while we were at it.
i += 8 - 2;
}
}
return true;
}
}
void ARMXEmitter::CMPI2R(ARMReg rs, u32 val, ARMReg scratch)
{
if (!TryCMPI2R(rs, val)) {
MOVI2R(scratch, val);
CMP(rs, scratch);
}
}
bool ARMXEmitter::TryCMPI2R(ARMReg rs, u32 val)
{
Operand2 op2;
bool negated;
if (TryMakeOperand2_AllowNegation(val, op2, &negated)) {
if (!negated)
CMP(rs, op2);
else
CMN(rs, op2);
return true;
} else {
return false;
}
}
void ARMXEmitter::TSTI2R(ARMReg rs, u32 val, ARMReg scratch)
{
if (!TryTSTI2R(rs, val)) {
MOVI2R(scratch, val);
TST(rs, scratch);
}
}
bool ARMXEmitter::TryTSTI2R(ARMReg rs, u32 val)
{
Operand2 op2;
if (TryMakeOperand2(val, op2)) {
TST(rs, op2);
return true;
} else {
return false;
}
}
void ARMXEmitter::ORI2R(ARMReg rd, ARMReg rs, u32 val, ARMReg scratch)
{
if (!TryORI2R(rd, rs, val)) {
MOVI2R(scratch, val);
ORR(rd, rs, scratch);
}
}
bool ARMXEmitter::TryORI2R(ARMReg rd, ARMReg rs, u32 val)
{
Operand2 op2;
if (val == 0) {
// Avoid the ALU, may improve pipeline.
if (rd != rs) {
MOV(rd, rs);
}
return true;
} else if (TryMakeOperand2(val, op2)) {
ORR(rd, rs, op2);
return true;
} else {
int ops = 0;
for (int i = 0; i < 32; i += 2) {
u8 bits = RotR(val, i) & 0xFF;
// If either low bit is set, we need to use a ORR for them.
if ((bits & 3) != 0) {
++ops;
i += 8 - 2;
}
}
// The worst case is 4 (e.g. 0x55555555.) But MVN can make it 2. Not sure if better.
bool inversed;
if (TryMakeOperand2_AllowInverse(val, op2, &inversed) && ops >= 3) {
return false;
#ifdef HAVE_ARMV7
} else if (ops > 3) {
return false;
#endif
}
bool first = true;
for (int i = 0; i < 32; i += 2) {
u8 bits = RotR(val, i) & 0xFF;
if ((bits & 3) != 0) {
u8 rotation = i == 0 ? 0 : 16 - i / 2;
if (first) {
ORR(rd, rs, Operand2(bits, rotation));
first = false;
} else {
ORR(rd, rd, Operand2(bits, rotation));
}
// Well, we took care of these other bits while we were at it.
i += 8 - 2;
}
}
return true;
}
}
void ARMXEmitter::EORI2R(ARMReg rd, ARMReg rs, u32 val, ARMReg scratch)
{
if (!TryEORI2R(rd, rs, val)) {
MOVI2R(scratch, val);
EOR(rd, rs, scratch);
}
}
bool ARMXEmitter::TryEORI2R(ARMReg rd, ARMReg rs, u32 val)
{
Operand2 op2;
if (val == 0) {
if (rd != rs) {
MOV(rd, rs);
}
return true;
} else if (TryMakeOperand2(val, op2)) {
EOR(rd, rs, op2);
return true;
} else {
return false;
}
}
void ARMXEmitter::FlushLitPool()
{
for (LiteralPool& pool : currentLitPool) {
// Search for duplicates
for (LiteralPool& old_pool : currentLitPool) {
if (old_pool.val == pool.val)
pool.loc = old_pool.loc;
}
// Write the constant to Literal Pool
if (!pool.loc)
{
pool.loc = (intptr_t)code;
Write32(pool.val);
}
s32 offset = (s32)(pool.loc - (intptr_t)pool.ldr_address - 8);
// Backpatch the LDR
*(u32*)pool.ldr_address |= (offset >= 0) << 23 | abs(offset);
}
// TODO: Save a copy of previous pools in case they are still in range.
currentLitPool.clear();
}
void ARMXEmitter::AddNewLit(u32 val)
{
LiteralPool pool_item;
pool_item.loc = 0;
pool_item.val = val;
pool_item.ldr_address = code;
currentLitPool.push_back(pool_item);
}
void ARMXEmitter::MOVI2R(ARMReg reg, u32 val, bool optimize)
{
Operand2 op2;
bool inverse;
#ifdef HAVE_ARMV7
// Unused
if (!optimize)
{
// For backpatching on ARMv7
MOVW(reg, val & 0xFFFF);
MOVT(reg, val, true);
return;
}
#endif
if (TryMakeOperand2_AllowInverse(val, op2, &inverse)) {
inverse ? MVN(reg, op2) : MOV(reg, op2);
} else {
#ifdef HAVE_ARMV7
// Use MOVW+MOVT for ARMv7+
MOVW(reg, val & 0xFFFF);
if(val & 0xFFFF0000)
MOVT(reg, val, true);
#else
if (!TrySetValue_TwoOp(reg,val)) {
bool first = true;
for (int i = 0; i < 32; i += 2) {
u8 bits = RotR(val, i) & 0xFF;
if ((bits & 3) != 0) {
u8 rotation = i == 0 ? 0 : 16 - i / 2;
if (first) {
MOV(reg, Operand2(bits, rotation));
first = false;
} else {
ORR(reg, reg, Operand2(bits, rotation));
}
// Well, we took care of these other bits while we were at it.
i += 8 - 2;
}
}
// Use literal pool for ARMv6.
// Disabled for now as it is crashfing since Vertex Decoder JIT
// AddNewLit(val);
// LDR(reg, R_PC); // To be backpatched later
}
#endif
}
}
static const char *armRegStrings[] = {
"r0","r1","r2","r3",
"r4","r5","r6","r7",
"r8","r9","r10","r11",
"r12","r13","r14","PC",
"s0", "s1", "s2", "s3",
"s4", "s5", "s6", "s7",
"s8", "s9", "s10", "s11",
"s12", "s13", "s14", "s15",
"s16", "s17", "s18", "s19",
"s20", "s21", "s22", "s23",
"s24", "s25", "s26", "s27",
"s28", "s29", "s30", "s31",
"d0", "d1", "d2", "d3",
"d4", "d5", "d6", "d7",
"d8", "d9", "d10", "d11",
"d12", "d13", "d14", "d15",
"d16", "d17", "d18", "d19",
"d20", "d21", "d22", "d23",
"d24", "d25", "d26", "d27",
"d28", "d29", "d30", "d31",
"q0", "q1", "q2", "q3",
"q4", "q5", "q6", "q7",
"q8", "q9", "q10", "q11",
"q12", "q13", "q14", "q15",
};
const char *ARMRegAsString(ARMReg reg) {
if ((unsigned int)reg >= sizeof(armRegStrings)/sizeof(armRegStrings[0]))
return "(bad)";
return armRegStrings[(int)reg];
}
void ARMXEmitter::QuickCallFunction(ARMReg reg, const void *func) {
if (BLInRange(func)) {
BL(func);
} else {
MOVP2R(reg, func);
BL(reg);
}
}
void ARMXEmitter::SetCodePointer(u8 *ptr)
{
code = ptr;
startcode = code;
lastCacheFlushEnd = ptr;
}
const u8 *ARMXEmitter::GetCodePointer() const
{
return code;
}
u8 *ARMXEmitter::GetWritableCodePtr()
{
return code;
}
void ARMXEmitter::ReserveCodeSpace(u32 bytes)
{
for (u32 i = 0; i < bytes/4; i++)
Write32(0xE1200070); //bkpt 0
}
const u8 *ARMXEmitter::AlignCode16()
{
ReserveCodeSpace((-(intptr_t)code) & 15);
return code;
}
const u8 *ARMXEmitter::AlignCodePage()
{
ReserveCodeSpace((-(intptr_t)code) & 4095);
return code;
}
void ARMXEmitter::FlushIcache()
{
FlushIcacheSection(lastCacheFlushEnd, code);
lastCacheFlushEnd = code;
}
void ARMXEmitter::FlushIcacheSection(u8 *start, u8 *end)
{
#if defined(IOS)
// Header file says this is equivalent to: sys_icache_invalidate(start, end - start);
sys_cache_control(kCacheFunctionPrepareForExecution, start, end - start);
#elif !defined(_WIN32)
#if defined(ARM)
#if defined(__clang__) || defined(ANDROID)
__clear_cache(start, end);
#else
__builtin___clear_cache(start, end);
#endif
#endif
#endif
}
void ARMXEmitter::SetCC(CCFlags cond)
{
condition = cond << 28;
}
void ARMXEmitter::NOP(int count)
{
for (int i = 0; i < count; i++) {
Write32(condition | 0x01A00000);
}
}
void ARMXEmitter::SETEND(bool BE)
{
//SETEND is non-conditional
Write32(0xF1010000 | (BE << 9));
}
void ARMXEmitter::BKPT(u16 arg)
{
Write32(condition | 0x01200070 | (arg << 4 & 0x000FFF00) | (arg & 0x0000000F));
}
void ARMXEmitter::YIELD()
{
Write32(condition | 0x0320F001);
}
FixupBranch ARMXEmitter::B()
{
FixupBranch branch;
branch.type = 0; // Zero for B
branch.ptr = code;
branch.condition = condition;
//We'll write NOP here for now.
Write32(condition | 0x01A00000);
return branch;
}
FixupBranch ARMXEmitter::BL()
{
FixupBranch branch;
branch.type = 1; // Zero for B
branch.ptr = code;
branch.condition = condition;
//We'll write NOP here for now.
Write32(condition | 0x01A00000);
return branch;
}
FixupBranch ARMXEmitter::B_CC(CCFlags Cond)
{
FixupBranch branch;
branch.type = 0; // Zero for B
branch.ptr = code;
branch.condition = Cond << 28;
//We'll write NOP here for now.
Write32(condition | 0x01A00000);
return branch;
}
void ARMXEmitter::B_CC(CCFlags Cond, const void *fnptr)
{
ptrdiff_t distance = (intptr_t)fnptr - ((intptr_t)(code) + 8);
_assert_msg_(JIT, distance > -0x2000000 && distance < 0x2000000,
"B_CC out of range (%p calls %p)", code, fnptr);
Write32((Cond << 28) | 0x0A000000 | ((distance >> 2) & 0x00FFFFFF));
}
FixupBranch ARMXEmitter::BL_CC(CCFlags Cond)
{
FixupBranch branch;
branch.type = 1; // Zero for B
branch.ptr = code;
branch.condition = Cond << 28;
//We'll write NOP here for now.
Write32(condition | 0x01A00000);
return branch;
}
void ARMXEmitter::SetJumpTarget(FixupBranch const &branch)
{
ptrdiff_t distance = ((intptr_t)(code) - 8) - (intptr_t)branch.ptr;
_assert_msg_(JIT, distance > -0x2000000 && distance < 0x2000000,
"SetJumpTarget out of range (%p calls %p)", code, branch.ptr);
u32 instr = (u32)(branch.condition | ((distance >> 2) & 0x00FFFFFF));
instr |= branch.type == 0 ? /* B */ 0x0A000000 : /* BL */ 0x0B000000;
*(u32*)branch.ptr = instr;
}
void ARMXEmitter::B(const void *fnptr)
{
ptrdiff_t distance = (intptr_t)fnptr - (intptr_t(code) + 8);
_assert_msg_(JIT, distance > -0x2000000 && distance < 0x2000000,
"B out of range (%p calls %p)", code, fnptr);
Write32(condition | 0x0A000000 | ((distance >> 2) & 0x00FFFFFF));
}
void ARMXEmitter::B(ARMReg src)
{
Write32(condition | 0x012FFF10 | src);
}
bool ARMXEmitter::BLInRange(const void *fnptr) const {
ptrdiff_t distance = (intptr_t)fnptr - (intptr_t(code) + 8);
if (distance <= -0x2000000 || distance >= 0x2000000)
return false;
else
return true;
}
void ARMXEmitter::BL(const void *fnptr)
{
ptrdiff_t distance = (intptr_t)fnptr - (intptr_t(code) + 8);
_assert_msg_(JIT, distance > -0x2000000 && distance < 0x2000000,
"BL out of range (%p calls %p)", code, fnptr);
Write32(condition | 0x0B000000 | ((distance >> 2) & 0x00FFFFFF));
}
void ARMXEmitter::BL(ARMReg src)
{
Write32(condition | 0x012FFF30 | src);
}
void ARMXEmitter::PUSH(const int num, ...)
{
u16 RegList = 0;
u8 Reg;
int i;
va_list vl;
va_start(vl, num);
for (i=0;i<num;i++)
{
Reg = va_arg(vl, u32);
RegList |= (1 << Reg);
}
va_end(vl);
Write32(condition | (2349 << 16) | RegList);
}
void ARMXEmitter::POP(const int num, ...)
{
u16 RegList = 0;
u8 Reg;
int i;
va_list vl;
va_start(vl, num);
for (i=0;i<num;i++)
{
Reg = va_arg(vl, u32);
RegList |= (1 << Reg);
}
va_end(vl);
Write32(condition | (2237 << 16) | RegList);
}
void ARMXEmitter::WriteShiftedDataOp(u32 op, bool SetFlags, ARMReg dest, ARMReg src, Operand2 op2)
{
Write32(condition | (13 << 21) | (SetFlags << 20) | (dest << 12) | op2.Imm5() | (op << 4) | src);
}
void ARMXEmitter::WriteShiftedDataOp(u32 op, bool SetFlags, ARMReg dest, ARMReg src, ARMReg op2)
{
Write32(condition | (13 << 21) | (SetFlags << 20) | (dest << 12) | (op2 << 8) | (op << 4) | src);
}
// IMM, REG, IMMSREG, RSR
// -1 for invalid if the instruction doesn't support that
const s32 InstOps[][4] = {{16, 0, 0, 0}, // AND(s)
{17, 1, 1, 1}, // EOR(s)
{18, 2, 2, 2}, // SUB(s)
{19, 3, 3, 3}, // RSB(s)
{20, 4, 4, 4}, // ADD(s)
{21, 5, 5, 5}, // ADC(s)
{22, 6, 6, 6}, // SBC(s)
{23, 7, 7, 7}, // RSC(s)
{24, 8, 8, 8}, // TST
{25, 9, 9, 9}, // TEQ
{26, 10, 10, 10}, // CMP
{27, 11, 11, 11}, // CMN
{28, 12, 12, 12}, // ORR(s)
{29, 13, 13, 13}, // MOV(s)
{30, 14, 14, 14}, // BIC(s)
{31, 15, 15, 15}, // MVN(s)
{24, -1, -1, -1}, // MOVW
{26, -1, -1, -1}, // MOVT
};
const char *InstNames[] = { "AND",
"EOR",
"SUB",
"RSB",
"ADD",
"ADC",
"SBC",
"RSC",
"TST",
"TEQ",
"CMP",
"CMN",
"ORR",
"MOV",
"BIC",
"MVN",
"MOVW",
"MOVT",
};
void ARMXEmitter::AND (ARMReg Rd, ARMReg Rn, Operand2 Rm) { WriteInstruction(0, Rd, Rn, Rm); }
void ARMXEmitter::ANDS(ARMReg Rd, ARMReg Rn, Operand2 Rm) { WriteInstruction(0, Rd, Rn, Rm, true); }
void ARMXEmitter::EOR (ARMReg Rd, ARMReg Rn, Operand2 Rm) { WriteInstruction(1, Rd, Rn, Rm); }
void ARMXEmitter::EORS(ARMReg Rd, ARMReg Rn, Operand2 Rm) { WriteInstruction(1, Rd, Rn, Rm, true); }
void ARMXEmitter::SUB (ARMReg Rd, ARMReg Rn, Operand2 Rm) { WriteInstruction(2, Rd, Rn, Rm); }
void ARMXEmitter::SUBS(ARMReg Rd, ARMReg Rn, Operand2 Rm) { WriteInstruction(2, Rd, Rn, Rm, true); }
void ARMXEmitter::RSB (ARMReg Rd, ARMReg Rn, Operand2 Rm) { WriteInstruction(3, Rd, Rn, Rm); }
void ARMXEmitter::RSBS(ARMReg Rd, ARMReg Rn, Operand2 Rm) { WriteInstruction(3, Rd, Rn, Rm, true); }
void ARMXEmitter::ADD (ARMReg Rd, ARMReg Rn, Operand2 Rm) { WriteInstruction(4, Rd, Rn, Rm); }
void ARMXEmitter::ADDS(ARMReg Rd, ARMReg Rn, Operand2 Rm) { WriteInstruction(4, Rd, Rn, Rm, true); }
void ARMXEmitter::ADC (ARMReg Rd, ARMReg Rn, Operand2 Rm) { WriteInstruction(5, Rd, Rn, Rm); }
void ARMXEmitter::ADCS(ARMReg Rd, ARMReg Rn, Operand2 Rm) { WriteInstruction(5, Rd, Rn, Rm, true); }
void ARMXEmitter::SBC (ARMReg Rd, ARMReg Rn, Operand2 Rm) { WriteInstruction(6, Rd, Rn, Rm); }
void ARMXEmitter::SBCS(ARMReg Rd, ARMReg Rn, Operand2 Rm) { WriteInstruction(6, Rd, Rn, Rm, true); }
void ARMXEmitter::RSC (ARMReg Rd, ARMReg Rn, Operand2 Rm) { WriteInstruction(7, Rd, Rn, Rm); }
void ARMXEmitter::RSCS(ARMReg Rd, ARMReg Rn, Operand2 Rm) { WriteInstruction(7, Rd, Rn, Rm, true); }
void ARMXEmitter::TST ( ARMReg Rn, Operand2 Rm) { WriteInstruction(8, R0, Rn, Rm, true); }
void ARMXEmitter::TEQ ( ARMReg Rn, Operand2 Rm) { WriteInstruction(9, R0, Rn, Rm, true); }
void ARMXEmitter::CMP ( ARMReg Rn, Operand2 Rm) { WriteInstruction(10, R0, Rn, Rm, true); }
void ARMXEmitter::CMN ( ARMReg Rn, Operand2 Rm) { WriteInstruction(11, R0, Rn, Rm, true); }
void ARMXEmitter::ORR (ARMReg Rd, ARMReg Rn, Operand2 Rm) { WriteInstruction(12, Rd, Rn, Rm); }
void ARMXEmitter::ORRS(ARMReg Rd, ARMReg Rn, Operand2 Rm) { WriteInstruction(12, Rd, Rn, Rm, true); }
void ARMXEmitter::MOV (ARMReg Rd, Operand2 Rm) { WriteInstruction(13, Rd, R0, Rm); }
void ARMXEmitter::MOVS(ARMReg Rd, Operand2 Rm) { WriteInstruction(13, Rd, R0, Rm, true); }
void ARMXEmitter::BIC (ARMReg Rd, ARMReg Rn, Operand2 Rm) { WriteInstruction(14, Rd, Rn, Rm); }
void ARMXEmitter::BICS(ARMReg Rd, ARMReg Rn, Operand2 Rm) { WriteInstruction(14, Rd, Rn, Rm, true); }
void ARMXEmitter::MVN (ARMReg Rd, Operand2 Rm) { WriteInstruction(15, Rd, R0, Rm); }
void ARMXEmitter::MVNS(ARMReg Rd, Operand2 Rm) { WriteInstruction(15, Rd, R0, Rm, true); }
void ARMXEmitter::MOVW(ARMReg Rd, Operand2 Rm) { WriteInstruction(16, Rd, R0, Rm); }
void ARMXEmitter::MOVT(ARMReg Rd, Operand2 Rm, bool TopBits) { WriteInstruction(17, Rd, R0, TopBits ? Rm.Value >> 16 : Rm); }
void ARMXEmitter::WriteInstruction (u32 Op, ARMReg Rd, ARMReg Rn, Operand2 Rm, bool SetFlags) // This can get renamed later
{
s32 op = InstOps[Op][Rm.GetType()]; // Type always decided by last operand
u32 Data = Rm.GetData();
if (Rm.GetType() == TYPE_IMM)
{
switch (Op)
{
// MOV cases that support IMM16
case 16:
case 17:
Data = Rm.Imm16();
break;
default:
break;
}
}
if (op == -1)
_assert_msg_(JIT, false, "%s not yet support %d", InstNames[Op], Rm.GetType());
Write32(condition | (op << 21) | (SetFlags ? (1 << 20) : 0) | Rn << 16 | Rd << 12 | Data);
}
// Data Operations
void ARMXEmitter::WriteSignedMultiply(u32 Op, u32 Op2, u32 Op3, ARMReg dest, ARMReg r1, ARMReg r2)
{
Write32(condition | (0x7 << 24) | (Op << 20) | (dest << 16) | (Op2 << 12) | (r1 << 8) | (Op3 << 5) | (1 << 4) | r2);
}
void ARMXEmitter::UDIV(ARMReg dest, ARMReg dividend, ARMReg divisor)
{
if (!cpu_info.bIDIVa)
PanicAlert("Trying to use integer divide on hardware that doesn't support it. Bad programmer.");
WriteSignedMultiply(3, 0xF, 0, dest, divisor, dividend);
}
void ARMXEmitter::SDIV(ARMReg dest, ARMReg dividend, ARMReg divisor)
{
if (!cpu_info.bIDIVa)
PanicAlert("Trying to use integer divide on hardware that doesn't support it. Bad programmer.");
WriteSignedMultiply(1, 0xF, 0, dest, divisor, dividend);
}
void ARMXEmitter::LSL (ARMReg dest, ARMReg src, Operand2 op2) { WriteShiftedDataOp(0, false, dest, src, op2);}
void ARMXEmitter::LSLS(ARMReg dest, ARMReg src, Operand2 op2) { WriteShiftedDataOp(0, true, dest, src, op2);}
void ARMXEmitter::LSL (ARMReg dest, ARMReg src, ARMReg op2) { WriteShiftedDataOp(1, false, dest, src, op2);}
void ARMXEmitter::LSLS(ARMReg dest, ARMReg src, ARMReg op2) { WriteShiftedDataOp(1, true, dest, src, op2);}
void ARMXEmitter::LSR (ARMReg dest, ARMReg src, Operand2 op2) {
_assert_msg_(JIT, op2.GetType() != TYPE_IMM || op2.Imm5() != 0, "LSR must have a non-zero shift (use LSL.)");
WriteShiftedDataOp(2, false, dest, src, op2);
}
void ARMXEmitter::LSRS(ARMReg dest, ARMReg src, Operand2 op2) {
_assert_msg_(JIT, op2.GetType() != TYPE_IMM || op2.Imm5() != 0, "LSRS must have a non-zero shift (use LSLS.)");
WriteShiftedDataOp(2, true, dest, src, op2);
}
void ARMXEmitter::LSR (ARMReg dest, ARMReg src, ARMReg op2) { WriteShiftedDataOp(3, false, dest, src, op2);}
void ARMXEmitter::LSRS(ARMReg dest, ARMReg src, ARMReg op2) { WriteShiftedDataOp(3, true, dest, src, op2);}
void ARMXEmitter::ASR (ARMReg dest, ARMReg src, Operand2 op2) {
_assert_msg_(JIT, op2.GetType() != TYPE_IMM || op2.Imm5() != 0, "ASR must have a non-zero shift (use LSL.)");
WriteShiftedDataOp(4, false, dest, src, op2);
}
void ARMXEmitter::ASRS(ARMReg dest, ARMReg src, Operand2 op2) {
_assert_msg_(JIT, op2.GetType() != TYPE_IMM || op2.Imm5() != 0, "ASRS must have a non-zero shift (use LSLS.)");
WriteShiftedDataOp(4, true, dest, src, op2);
}
void ARMXEmitter::ASR (ARMReg dest, ARMReg src, ARMReg op2) { WriteShiftedDataOp(5, false, dest, src, op2);}
void ARMXEmitter::ASRS(ARMReg dest, ARMReg src, ARMReg op2) { WriteShiftedDataOp(5, true, dest, src, op2);}
void ARMXEmitter::MUL (ARMReg dest, ARMReg src, ARMReg op2)
{
Write32(condition | (dest << 16) | (src << 8) | (9 << 4) | op2);
}
void ARMXEmitter::MULS(ARMReg dest, ARMReg src, ARMReg op2)
{
Write32(condition | (1 << 20) | (dest << 16) | (src << 8) | (9 << 4) | op2);
}
void ARMXEmitter::Write4OpMultiply(u32 op, ARMReg destLo, ARMReg destHi, ARMReg rm, ARMReg rn) {
Write32(condition | (op << 20) | (destHi << 16) | (destLo << 12) | (rm << 8) | (9 << 4) | rn);
}
void ARMXEmitter::UMULL(ARMReg destLo, ARMReg destHi, ARMReg rm, ARMReg rn)
{
Write4OpMultiply(0x8, destLo, destHi, rn, rm);
}
void ARMXEmitter::SMULL(ARMReg destLo, ARMReg destHi, ARMReg rm, ARMReg rn)
{
Write4OpMultiply(0xC, destLo, destHi, rn, rm);
}
void ARMXEmitter::UMLAL(ARMReg destLo, ARMReg destHi, ARMReg rm, ARMReg rn)
{
Write4OpMultiply(0xA, destLo, destHi, rn, rm);
}
void ARMXEmitter::SMLAL(ARMReg destLo, ARMReg destHi, ARMReg rm, ARMReg rn)
{
Write4OpMultiply(0xE, destLo, destHi, rn, rm);
}
void ARMXEmitter::UBFX(ARMReg dest, ARMReg rn, u8 lsb, u8 width)
{
Write32(condition | (0x7E0 << 16) | ((width - 1) << 16) | (dest << 12) | (lsb << 7) | (5 << 4) | rn);
}
void ARMXEmitter::SBFX(ARMReg dest, ARMReg rn, u8 lsb, u8 width)
{
Write32(condition | (0x7A0 << 16) | ((width - 1) << 16) | (dest << 12) | (lsb << 7) | (5 << 4) | rn);
}
void ARMXEmitter::CLZ(ARMReg rd, ARMReg rm)
{
Write32(condition | (0x16F << 16) | (rd << 12) | (0xF1 << 4) | rm);
}
void ARMXEmitter::PLD(ARMReg rn, int offset, bool forWrite) {
_dbg_assert_msg_(JIT, offset < 0x3ff && offset > -0x3ff, "PLD: Max 12 bits of offset allowed");
bool U = offset >= 0;
if (offset < 0) offset = -offset;
bool R = !forWrite;
// Conditions not allowed
Write32((0xF5 << 24) | (U << 23) | (R << 22) | (1 << 20) | ((int)rn << 16) | (0xF << 12) | offset);
}
void ARMXEmitter::BFI(ARMReg rd, ARMReg rn, u8 lsb, u8 width)
{
u32 msb = (lsb + width - 1);
if (msb > 31) msb = 31;
Write32(condition | (0x7C0 << 16) | (msb << 16) | (rd << 12) | (lsb << 7) | (1 << 4) | rn);
}