Merge branch 'zminhquanz-cpu-detection'

hrydgard · Sep 14, 2018 · 66e13f7 · 66e13f7
2 parents a1e33fd + 49e2a2d
commit 66e13f7
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Showing 2 changed files with 41 additions and 14 deletions.
diff --git a/Common/CPUDetect.cpp b/Common/CPUDetect.cpp
@@ -15,6 +15,7 @@
 // Official SVN repository and contact information can be found at
 // http://code.google.com/p/dolphin-emu/
 
+// Reference : https://stackoverflow.com/questions/6121792/how-to-check-if-a-cpu-supports-the-sse3-instruction-set
 #if defined(_M_IX86) || defined(_M_X64)
 
 #include "ppsspp_config.h"
@@ -198,7 +199,7 @@ void CPUInfo::Detect() {
 		if ((cpu_id[2] >> 28) & 1) {
 			bAVX = true;
 			if ((cpu_id[2] >> 12) & 1)
-				bFMA = true;
+				bFMA3 = true;
 		}
 		if ((cpu_id[2] >> 25) & 1) bAES = true;
 
@@ -219,10 +220,15 @@ void CPUInfo::Detect() {
 			{
 				bAVX = true;
 				if ((cpu_id[2] >> 12) & 1)
-					bFMA = true;
+					bFMA3 = true;
 			}
 		}
 
+
+		// TSX support require check:
+		// -- Is the RTM bit set in CPUID? (>>11)
+		// -- No need to check HLE bit because legacy processors ignore HLE hints
+		// -- See https://software.intel.com/en-us/articles/how-to-detect-new-instruction-support-in-the-4th-generation-intel-core-processor-family
 		if (max_std_fn >= 7)
 		{
 			do_cpuid(cpu_id, 0x00000007);
@@ -233,6 +239,10 @@ void CPUInfo::Detect() {
 				bBMI1 = true;
 			if ((cpu_id[1] >> 8) & 1)
 				bBMI2 = true;
+			if ((cpu_id[1] >> 29) & 1)
+				bSHA = true;
+			if ((cpu_id[1] >> 11) & 1)
+				bRTM = true;
 		}
 	}
 	if (max_ex_fn >= 0x80000004) {
@@ -248,6 +258,9 @@ void CPUInfo::Detect() {
 		// Check for more features.
 		do_cpuid(cpu_id, 0x80000001);
 		if (cpu_id[2] & 1) bLAHFSAHF64 = true;
+		if ((cpu_id[2] >> 6) & 1) bSSE4A = true;
+		if ((cpu_id[2] >> 16) & 1) bFMA4 = true;
+		if ((cpu_id[2] >> 11) & 1) bXOP = true;
 		// CmpLegacy (bit 2) is deprecated.
 		if ((cpu_id[3] >> 29) & 1) bLongMode = true;
 	}
@@ -404,10 +417,16 @@ std::string CPUInfo::Summarize()
 	if (bSSSE3) sum += ", SSSE3";
 	if (bSSE4_1) sum += ", SSE4.1";
 	if (bSSE4_2) sum += ", SSE4.2";
+	if (bSSE4A) sum += ", SSE4A";
 	if (HTT) sum += ", HTT";
 	if (bAVX) sum += ", AVX";
-	if (bFMA) sum += ", FMA";
+	if (bAVX2) sum += ", AVX2";
+	if (bFMA3) sum += ", FMA3";
+	if (bFMA4) sum += ", FMA4";
 	if (bAES) sum += ", AES";
+	if (bSHA) sum += ", SHA";
+	if (bXOP) sum += ", XOP";
+	if (bRTM) sum += ", TSX";
 	if (bLongMode) sum += ", 64-bit support";
 	return sum;
 }

diff --git a/Common/CPUDetect.h b/Common/CPUDetect.h
@@ -31,6 +31,7 @@ enum CPUVendor {
 struct CPUInfo {
 	CPUVendor vendor;
 
+	// Misc
 	char cpu_string[0x21];
 	char brand_string[0x41];
 	bool OS64bit;
@@ -41,26 +42,33 @@ struct CPUInfo {
 	int num_cores;
 	int logical_cpu_count;
 
+	bool bAtom;
+	bool bPOPCNT;
+	bool bLAHFSAHF64;
+	bool bLongMode;
+	bool bMOVBE;
+	bool bFXSR;
+	bool bLZCNT;
+	bool bBMI1;
+	bool bBMI2;
+	bool bXOP;
+	bool bRTM;
+
+	// x86 : SIMD 128 bit
 	bool bSSE;
 	bool bSSE2;
 	bool bSSE3;
 	bool bSSSE3;
-	bool bPOPCNT;
 	bool bSSE4_1;
 	bool bSSE4_2;
-	bool bLZCNT;
 	bool bSSE4A;
+	bool bAES;
+	bool bSHA;
+	// x86 : SIMD 256 bit
 	bool bAVX;
 	bool bAVX2;
-	bool bFMA;
+	bool bFMA3;
-	bool bAES;
+	bool bFMA4;
-	bool bLAHFSAHF64;
-	bool bLongMode;
-	bool bAtom;
-	bool bBMI1;
-	bool bBMI2;
-	bool bMOVBE;
-	bool bFXSR;
 
 	// ARM specific CPUInfo
 	bool bSwp;