/
asm7.go
4158 lines (3361 loc) · 91.3 KB
/
asm7.go
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// cmd/7l/asm.c, cmd/7l/asmout.c, cmd/7l/optab.c, cmd/7l/span.c, cmd/ld/sub.c, cmd/ld/mod.c, from Vita Nuova.
// https://code.google.com/p/ken-cc/source/browse/
//
// Copyright © 1994-1999 Lucent Technologies Inc. All rights reserved.
// Portions Copyright © 1995-1997 C H Forsyth (forsyth@terzarima.net)
// Portions Copyright © 1997-1999 Vita Nuova Limited
// Portions Copyright © 2000-2007 Vita Nuova Holdings Limited (www.vitanuova.com)
// Portions Copyright © 2004,2006 Bruce Ellis
// Portions Copyright © 2005-2007 C H Forsyth (forsyth@terzarima.net)
// Revisions Copyright © 2000-2007 Lucent Technologies Inc. and others
// Portions Copyright © 2009 The Go Authors. All rights reserved.
//
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
package arm64
import (
"cmd/internal/obj"
"fmt"
"log"
"math"
"sort"
)
const (
FuncAlign = 16
)
const (
REGFROM = 1
)
type Optab struct {
as uint16
a1 uint8
a2 uint8
a3 uint8
type_ int8
size int8
param int16
flag int8
scond uint16
}
type Oprange struct {
start []Optab
stop []Optab
}
var oprange [ALAST]Oprange
var xcmp [C_NCLASS][C_NCLASS]uint8
const (
S32 = 0 << 31
S64 = 1 << 31
Sbit = 1 << 29
LSL0_32 = 2 << 13
LSL0_64 = 3 << 13
)
func OPDP2(x uint32) uint32 {
return 0<<30 | 0<<29 | 0xd6<<21 | x<<10
}
func OPDP3(sf uint32, op54 uint32, op31 uint32, o0 uint32) uint32 {
return sf<<31 | op54<<29 | 0x1B<<24 | op31<<21 | o0<<15
}
func OPBcc(x uint32) uint32 {
return 0x2A<<25 | 0<<24 | 0<<4 | x&15
}
func OPBLR(x uint32) uint32 {
/* x=0, JMP; 1, CALL; 2, RET */
return 0x6B<<25 | 0<<23 | x<<21 | 0x1F<<16 | 0<<10
}
func SYSOP(l uint32, op0 uint32, op1 uint32, crn uint32, crm uint32, op2 uint32, rt uint32) uint32 {
return 0x354<<22 | l<<21 | op0<<19 | op1<<16 | crn&15<<12 | crm&15<<8 | op2<<5 | rt
}
func SYSHINT(x uint32) uint32 {
return SYSOP(0, 0, 3, 2, 0, x, 0x1F)
}
func LDSTR12U(sz uint32, v uint32, opc uint32) uint32 {
return sz<<30 | 7<<27 | v<<26 | 1<<24 | opc<<22
}
func LDSTR9S(sz uint32, v uint32, opc uint32) uint32 {
return sz<<30 | 7<<27 | v<<26 | 0<<24 | opc<<22
}
func LD2STR(o uint32) uint32 {
return o &^ (3 << 22)
}
func LDSTX(sz uint32, o2 uint32, l uint32, o1 uint32, o0 uint32) uint32 {
return sz<<30 | 0x8<<24 | o2<<23 | l<<22 | o1<<21 | o0<<15
}
func FPCMP(m uint32, s uint32, type_ uint32, op uint32, op2 uint32) uint32 {
return m<<31 | s<<29 | 0x1E<<24 | type_<<22 | 1<<21 | op<<14 | 8<<10 | op2
}
func FPCCMP(m uint32, s uint32, type_ uint32, op uint32) uint32 {
return m<<31 | s<<29 | 0x1E<<24 | type_<<22 | 1<<21 | 1<<10 | op<<4
}
func FPOP1S(m uint32, s uint32, type_ uint32, op uint32) uint32 {
return m<<31 | s<<29 | 0x1E<<24 | type_<<22 | 1<<21 | op<<15 | 0x10<<10
}
func FPOP2S(m uint32, s uint32, type_ uint32, op uint32) uint32 {
return m<<31 | s<<29 | 0x1E<<24 | type_<<22 | 1<<21 | op<<12 | 2<<10
}
func FPCVTI(sf uint32, s uint32, type_ uint32, rmode uint32, op uint32) uint32 {
return sf<<31 | s<<29 | 0x1E<<24 | type_<<22 | 1<<21 | rmode<<19 | op<<16 | 0<<10
}
func ADR(p uint32, o uint32, rt uint32) uint32 {
return p<<31 | (o&3)<<29 | 0x10<<24 | ((o>>2)&0x7FFFF)<<5 | rt&31
}
func OPBIT(x uint32) uint32 {
return 1<<30 | 0<<29 | 0xD6<<21 | 0<<16 | x<<10
}
const (
LFROM = 1 << 0
LTO = 1 << 1
LPOOL = 1 << 2
)
var optab = []Optab{
/* struct Optab:
OPCODE, from, prog->reg, to, type,size,param,flag,scond */
{obj.ATEXT, C_ADDR, C_NONE, C_TEXTSIZE, 0, 0, 0, 0, 0},
/* arithmetic operations */
{AADD, C_REG, C_REG, C_REG, 1, 4, 0, 0, 0},
{AADD, C_REG, C_NONE, C_REG, 1, 4, 0, 0, 0},
{AADC, C_REG, C_REG, C_REG, 1, 4, 0, 0, 0},
{AADC, C_REG, C_NONE, C_REG, 1, 4, 0, 0, 0},
{ANEG, C_REG, C_NONE, C_REG, 25, 4, 0, 0, 0},
{ANGC, C_REG, C_NONE, C_REG, 17, 4, 0, 0, 0},
{ACMP, C_REG, C_REG, C_NONE, 1, 4, 0, 0, 0},
{AADD, C_ADDCON, C_RSP, C_RSP, 2, 4, 0, 0, 0},
{AADD, C_ADDCON, C_NONE, C_RSP, 2, 4, 0, 0, 0},
{ACMP, C_ADDCON, C_RSP, C_NONE, 2, 4, 0, 0, 0},
// TODO: these don't work properly.
// {AADD, C_MBCON, C_RSP, C_RSP, 2, 4, 0, 0, 0},
// {AADD, C_MBCON, C_NONE, C_RSP, 2, 4, 0, 0, 0},
// {ACMP, C_MBCON, C_RSP, C_NONE, 2, 4, 0, 0, 0},
{AADD, C_VCON, C_RSP, C_RSP, 13, 8, 0, LFROM, 0},
{AADD, C_VCON, C_NONE, C_RSP, 13, 8, 0, LFROM, 0},
{ACMP, C_VCON, C_REG, C_NONE, 13, 8, 0, LFROM, 0},
{AADD, C_SHIFT, C_REG, C_REG, 3, 4, 0, 0, 0},
{AADD, C_SHIFT, C_NONE, C_REG, 3, 4, 0, 0, 0},
{AMVN, C_SHIFT, C_NONE, C_REG, 3, 4, 0, 0, 0},
{ACMP, C_SHIFT, C_REG, C_NONE, 3, 4, 0, 0, 0},
{ANEG, C_SHIFT, C_NONE, C_REG, 26, 4, 0, 0, 0},
{AADD, C_REG, C_RSP, C_RSP, 27, 4, 0, 0, 0},
{AADD, C_REG, C_NONE, C_RSP, 27, 4, 0, 0, 0},
{ACMP, C_REG, C_RSP, C_NONE, 27, 4, 0, 0, 0},
{AADD, C_EXTREG, C_RSP, C_RSP, 27, 4, 0, 0, 0},
{AADD, C_EXTREG, C_NONE, C_RSP, 27, 4, 0, 0, 0},
{AMVN, C_EXTREG, C_NONE, C_RSP, 27, 4, 0, 0, 0},
{ACMP, C_EXTREG, C_RSP, C_NONE, 27, 4, 0, 0, 0},
{AADD, C_REG, C_REG, C_REG, 1, 4, 0, 0, 0},
{AADD, C_REG, C_NONE, C_REG, 1, 4, 0, 0, 0},
/* logical operations */
{AAND, C_REG, C_REG, C_REG, 1, 4, 0, 0, 0},
{AAND, C_REG, C_NONE, C_REG, 1, 4, 0, 0, 0},
{ABIC, C_REG, C_REG, C_REG, 1, 4, 0, 0, 0},
{ABIC, C_REG, C_NONE, C_REG, 1, 4, 0, 0, 0},
// TODO: these don't work properly.
// {AAND, C_BITCON, C_REG, C_REG, 53, 4, 0, 0, 0},
// {AAND, C_BITCON, C_NONE, C_REG, 53, 4, 0, 0, 0},
// {ABIC, C_BITCON, C_REG, C_REG, 53, 4, 0, 0, 0},
// {ABIC, C_BITCON, C_NONE, C_REG, 53, 4, 0, 0, 0},
{AAND, C_VCON, C_REG, C_REG, 28, 8, 0, LFROM, 0},
{AAND, C_VCON, C_NONE, C_REG, 28, 8, 0, LFROM, 0},
{ABIC, C_VCON, C_REG, C_REG, 28, 8, 0, LFROM, 0},
{ABIC, C_VCON, C_NONE, C_REG, 28, 8, 0, LFROM, 0},
{AAND, C_SHIFT, C_REG, C_REG, 3, 4, 0, 0, 0},
{AAND, C_SHIFT, C_NONE, C_REG, 3, 4, 0, 0, 0},
{ABIC, C_SHIFT, C_REG, C_REG, 3, 4, 0, 0, 0},
{ABIC, C_SHIFT, C_NONE, C_REG, 3, 4, 0, 0, 0},
{AMOVD, C_RSP, C_NONE, C_RSP, 24, 4, 0, 0, 0},
{AMVN, C_REG, C_NONE, C_REG, 24, 4, 0, 0, 0},
{AMOVB, C_REG, C_NONE, C_REG, 45, 4, 0, 0, 0},
{AMOVBU, C_REG, C_NONE, C_REG, 45, 4, 0, 0, 0},
{AMOVH, C_REG, C_NONE, C_REG, 45, 4, 0, 0, 0}, /* also MOVHU */
{AMOVW, C_REG, C_NONE, C_REG, 45, 4, 0, 0, 0}, /* also MOVWU */
/* TODO: MVN C_SHIFT */
/* MOVs that become MOVK/MOVN/MOVZ/ADD/SUB/OR */
{AMOVW, C_MOVCON, C_NONE, C_REG, 32, 4, 0, 0, 0},
{AMOVD, C_MOVCON, C_NONE, C_REG, 32, 4, 0, 0, 0},
// TODO: these don't work properly.
// { AMOVW, C_ADDCON, C_NONE, C_REG, 2, 4, 0 , 0},
// { AMOVD, C_ADDCON, C_NONE, C_REG, 2, 4, 0 , 0},
// { AMOVW, C_BITCON, C_NONE, C_REG, 53, 4, 0 , 0},
// { AMOVD, C_BITCON, C_NONE, C_REG, 53, 4, 0 , 0},
{AMOVK, C_VCON, C_NONE, C_REG, 33, 4, 0, 0, 0},
{AMOVD, C_AACON, C_NONE, C_REG, 4, 4, REGFROM, 0, 0},
{ASDIV, C_REG, C_NONE, C_REG, 1, 4, 0, 0, 0},
{ASDIV, C_REG, C_REG, C_REG, 1, 4, 0, 0, 0},
{AB, C_NONE, C_NONE, C_SBRA, 5, 4, 0, 0, 0},
{ABL, C_NONE, C_NONE, C_SBRA, 5, 4, 0, 0, 0},
{AB, C_NONE, C_NONE, C_ZOREG, 6, 4, 0, 0, 0},
{ABL, C_NONE, C_NONE, C_REG, 6, 4, 0, 0, 0},
{ABL, C_REG, C_NONE, C_REG, 6, 4, 0, 0, 0},
{ABL, C_NONE, C_NONE, C_ZOREG, 6, 4, 0, 0, 0},
{obj.ARET, C_NONE, C_NONE, C_REG, 6, 4, 0, 0, 0},
{obj.ARET, C_NONE, C_NONE, C_ZOREG, 6, 4, 0, 0, 0},
{AADRP, C_SBRA, C_NONE, C_REG, 60, 4, 0, 0, 0},
{AADR, C_SBRA, C_NONE, C_REG, 61, 4, 0, 0, 0},
{ABFM, C_VCON, C_REG, C_REG, 42, 4, 0, 0, 0},
{ABFI, C_VCON, C_REG, C_REG, 43, 4, 0, 0, 0},
{AEXTR, C_VCON, C_REG, C_REG, 44, 4, 0, 0, 0},
{ASXTB, C_REG, C_NONE, C_REG, 45, 4, 0, 0, 0},
{ACLS, C_REG, C_NONE, C_REG, 46, 4, 0, 0, 0},
{ABEQ, C_NONE, C_NONE, C_SBRA, 7, 4, 0, 0, 0},
{ALSL, C_VCON, C_REG, C_REG, 8, 4, 0, 0, 0},
{ALSL, C_VCON, C_NONE, C_REG, 8, 4, 0, 0, 0},
{ALSL, C_REG, C_NONE, C_REG, 9, 4, 0, 0, 0},
{ALSL, C_REG, C_REG, C_REG, 9, 4, 0, 0, 0},
{ASVC, C_NONE, C_NONE, C_VCON, 10, 4, 0, 0, 0},
{ASVC, C_NONE, C_NONE, C_NONE, 10, 4, 0, 0, 0},
{ADWORD, C_NONE, C_NONE, C_VCON, 11, 8, 0, 0, 0},
{ADWORD, C_NONE, C_NONE, C_LEXT, 11, 8, 0, 0, 0},
{ADWORD, C_NONE, C_NONE, C_ADDR, 11, 8, 0, 0, 0},
{ADWORD, C_NONE, C_NONE, C_LACON, 11, 8, 0, 0, 0},
{AWORD, C_NONE, C_NONE, C_LCON, 14, 4, 0, 0, 0},
{AWORD, C_NONE, C_NONE, C_LEXT, 14, 4, 0, 0, 0},
{AWORD, C_NONE, C_NONE, C_ADDR, 14, 4, 0, 0, 0},
{AMOVW, C_VCON, C_NONE, C_REG, 12, 4, 0, LFROM, 0},
{AMOVW, C_VCONADDR, C_NONE, C_REG, 68, 8, 0, 0, 0},
{AMOVD, C_VCON, C_NONE, C_REG, 12, 4, 0, LFROM, 0},
{AMOVD, C_VCONADDR, C_NONE, C_REG, 68, 8, 0, 0, 0},
{AMOVB, C_REG, C_NONE, C_ADDR, 64, 12, 0, 0, 0},
{AMOVBU, C_REG, C_NONE, C_ADDR, 64, 12, 0, 0, 0},
{AMOVH, C_REG, C_NONE, C_ADDR, 64, 12, 0, 0, 0},
{AMOVW, C_REG, C_NONE, C_ADDR, 64, 12, 0, 0, 0},
{AMOVD, C_REG, C_NONE, C_ADDR, 64, 12, 0, 0, 0},
{AMOVB, C_ADDR, C_NONE, C_REG, 65, 12, 0, 0, 0},
{AMOVBU, C_ADDR, C_NONE, C_REG, 65, 12, 0, 0, 0},
{AMOVH, C_ADDR, C_NONE, C_REG, 65, 12, 0, 0, 0},
{AMOVW, C_ADDR, C_NONE, C_REG, 65, 12, 0, 0, 0},
{AMOVD, C_ADDR, C_NONE, C_REG, 65, 12, 0, 0, 0},
{AMUL, C_REG, C_REG, C_REG, 15, 4, 0, 0, 0},
{AMUL, C_REG, C_NONE, C_REG, 15, 4, 0, 0, 0},
{AMADD, C_REG, C_REG, C_REG, 15, 4, 0, 0, 0},
{AREM, C_REG, C_REG, C_REG, 16, 8, 0, 0, 0},
{AREM, C_REG, C_NONE, C_REG, 16, 8, 0, 0, 0},
{ACSEL, C_COND, C_REG, C_REG, 18, 4, 0, 0, 0}, /* from3 optional */
{ACSET, C_COND, C_NONE, C_REG, 18, 4, 0, 0, 0},
{ACCMN, C_COND, C_REG, C_VCON, 19, 4, 0, 0, 0}, /* from3 either C_REG or C_VCON */
/* scaled 12-bit unsigned displacement store */
{AMOVB, C_REG, C_NONE, C_UAUTO4K, 20, 4, REGSP, 0, 0},
{AMOVB, C_REG, C_NONE, C_UOREG4K, 20, 4, 0, 0, 0},
{AMOVBU, C_REG, C_NONE, C_UAUTO4K, 20, 4, REGSP, 0, 0},
{AMOVBU, C_REG, C_NONE, C_UOREG4K, 20, 4, 0, 0, 0},
{AMOVH, C_REG, C_NONE, C_UAUTO8K, 20, 4, REGSP, 0, 0},
{AMOVH, C_REG, C_NONE, C_ZOREG, 20, 4, 0, 0, 0},
{AMOVH, C_REG, C_NONE, C_UOREG8K, 20, 4, 0, 0, 0},
{AMOVW, C_REG, C_NONE, C_UAUTO16K, 20, 4, REGSP, 0, 0},
{AMOVW, C_REG, C_NONE, C_ZOREG, 20, 4, 0, 0, 0},
{AMOVW, C_REG, C_NONE, C_UOREG16K, 20, 4, 0, 0, 0},
/* unscaled 9-bit signed displacement store */
{AMOVB, C_REG, C_NONE, C_NSAUTO, 20, 4, REGSP, 0, 0},
{AMOVB, C_REG, C_NONE, C_NSOREG, 20, 4, 0, 0, 0},
{AMOVBU, C_REG, C_NONE, C_NSAUTO, 20, 4, REGSP, 0, 0},
{AMOVBU, C_REG, C_NONE, C_NSOREG, 20, 4, 0, 0, 0},
{AMOVH, C_REG, C_NONE, C_NSAUTO, 20, 4, REGSP, 0, 0},
{AMOVH, C_REG, C_NONE, C_NSOREG, 20, 4, 0, 0, 0},
{AMOVW, C_REG, C_NONE, C_NSAUTO, 20, 4, REGSP, 0, 0},
{AMOVW, C_REG, C_NONE, C_NSOREG, 20, 4, 0, 0, 0},
{AMOVD, C_REG, C_NONE, C_UAUTO32K, 20, 4, REGSP, 0, 0},
{AMOVD, C_REG, C_NONE, C_ZOREG, 20, 4, 0, 0, 0},
{AMOVD, C_REG, C_NONE, C_UOREG32K, 20, 4, 0, 0, 0},
{AMOVD, C_REG, C_NONE, C_NSOREG, 20, 4, 0, 0, 0},
{AMOVD, C_REG, C_NONE, C_NSAUTO, 20, 4, REGSP, 0, 0},
/* short displacement load */
{AMOVB, C_UAUTO4K, C_NONE, C_REG, 21, 4, REGSP, 0, 0},
{AMOVB, C_NSAUTO, C_NONE, C_REG, 21, 4, REGSP, 0, 0},
{AMOVB, C_ZOREG, C_NONE, C_REG, 21, 4, 0, 0, 0},
{AMOVB, C_UOREG4K, C_NONE, C_REG, 21, 4, REGSP, 0, 0},
{AMOVB, C_NSOREG, C_NONE, C_REG, 21, 4, REGSP, 0, 0},
{AMOVBU, C_UAUTO4K, C_NONE, C_REG, 21, 4, REGSP, 0, 0},
{AMOVBU, C_NSAUTO, C_NONE, C_REG, 21, 4, REGSP, 0, 0},
{AMOVBU, C_ZOREG, C_NONE, C_REG, 21, 4, 0, 0, 0},
{AMOVBU, C_UOREG4K, C_NONE, C_REG, 21, 4, REGSP, 0, 0},
{AMOVBU, C_NSOREG, C_NONE, C_REG, 21, 4, REGSP, 0, 0},
{AMOVH, C_UAUTO8K, C_NONE, C_REG, 21, 4, REGSP, 0, 0},
{AMOVH, C_NSAUTO, C_NONE, C_REG, 21, 4, REGSP, 0, 0},
{AMOVH, C_ZOREG, C_NONE, C_REG, 21, 4, 0, 0, 0},
{AMOVH, C_UOREG8K, C_NONE, C_REG, 21, 4, REGSP, 0, 0},
{AMOVH, C_NSOREG, C_NONE, C_REG, 21, 4, REGSP, 0, 0},
{AMOVW, C_UAUTO16K, C_NONE, C_REG, 21, 4, REGSP, 0, 0},
{AMOVW, C_NSAUTO, C_NONE, C_REG, 21, 4, REGSP, 0, 0},
{AMOVW, C_ZOREG, C_NONE, C_REG, 21, 4, 0, 0, 0},
{AMOVW, C_UOREG16K, C_NONE, C_REG, 21, 4, REGSP, 0, 0},
{AMOVW, C_NSOREG, C_NONE, C_REG, 21, 4, REGSP, 0, 0},
{AMOVD, C_UAUTO32K, C_NONE, C_REG, 21, 4, REGSP, 0, 0},
{AMOVD, C_NSAUTO, C_NONE, C_REG, 21, 4, REGSP, 0, 0},
{AMOVD, C_ZOREG, C_NONE, C_REG, 21, 4, 0, 0, 0},
{AMOVD, C_UOREG32K, C_NONE, C_REG, 21, 4, REGSP, 0, 0},
{AMOVD, C_NSOREG, C_NONE, C_REG, 21, 4, REGSP, 0, 0},
/* long displacement store */
{AMOVB, C_REG, C_NONE, C_LAUTO, 30, 8, REGSP, 0, 0},
{AMOVB, C_REG, C_NONE, C_LOREG, 30, 8, 0, 0, 0},
{AMOVBU, C_REG, C_NONE, C_LAUTO, 30, 8, REGSP, 0, 0},
{AMOVBU, C_REG, C_NONE, C_LOREG, 30, 8, 0, 0, 0},
{AMOVH, C_REG, C_NONE, C_LAUTO, 30, 8, REGSP, 0, 0},
{AMOVH, C_REG, C_NONE, C_LOREG, 30, 8, 0, 0, 0},
{AMOVW, C_REG, C_NONE, C_LAUTO, 30, 8, REGSP, 0, 0},
{AMOVW, C_REG, C_NONE, C_LOREG, 30, 8, 0, 0, 0},
{AMOVD, C_REG, C_NONE, C_LAUTO, 30, 8, REGSP, 0, 0},
{AMOVD, C_REG, C_NONE, C_LOREG, 30, 8, 0, 0, 0},
/* long displacement load */
{AMOVB, C_LAUTO, C_NONE, C_REG, 31, 8, REGSP, 0, 0},
{AMOVB, C_LOREG, C_NONE, C_REG, 31, 8, 0, 0, 0},
{AMOVB, C_LOREG, C_NONE, C_REG, 31, 8, 0, 0, 0},
{AMOVBU, C_LAUTO, C_NONE, C_REG, 31, 8, REGSP, 0, 0},
{AMOVBU, C_LOREG, C_NONE, C_REG, 31, 8, 0, 0, 0},
{AMOVBU, C_LOREG, C_NONE, C_REG, 31, 8, 0, 0, 0},
{AMOVH, C_LAUTO, C_NONE, C_REG, 31, 8, REGSP, 0, 0},
{AMOVH, C_LOREG, C_NONE, C_REG, 31, 8, 0, 0, 0},
{AMOVH, C_LOREG, C_NONE, C_REG, 31, 8, 0, 0, 0},
{AMOVW, C_LAUTO, C_NONE, C_REG, 31, 8, REGSP, 0, 0},
{AMOVW, C_LOREG, C_NONE, C_REG, 31, 8, 0, 0, 0},
{AMOVW, C_LOREG, C_NONE, C_REG, 31, 8, 0, 0, 0},
{AMOVD, C_LAUTO, C_NONE, C_REG, 31, 8, REGSP, 0, 0},
{AMOVD, C_LOREG, C_NONE, C_REG, 31, 8, 0, 0, 0},
{AMOVD, C_LOREG, C_NONE, C_REG, 31, 8, 0, 0, 0},
/* load long effective stack address (load int32 offset and add) */
{AMOVD, C_LACON, C_NONE, C_REG, 34, 8, REGSP, LFROM, 0},
/* pre/post-indexed load (unscaled, signed 9-bit offset) */
{AMOVD, C_LOREG, C_NONE, C_REG, 22, 4, 0, 0, C_XPOST},
{AMOVW, C_LOREG, C_NONE, C_REG, 22, 4, 0, 0, C_XPOST},
{AMOVH, C_LOREG, C_NONE, C_REG, 22, 4, 0, 0, C_XPOST},
{AMOVB, C_LOREG, C_NONE, C_REG, 22, 4, 0, 0, C_XPOST},
{AMOVBU, C_LOREG, C_NONE, C_REG, 22, 4, 0, 0, C_XPOST},
{AFMOVS, C_LOREG, C_NONE, C_FREG, 22, 4, 0, 0, C_XPOST},
{AFMOVD, C_LOREG, C_NONE, C_FREG, 22, 4, 0, 0, C_XPOST},
{AMOVD, C_LOREG, C_NONE, C_REG, 22, 4, 0, 0, C_XPRE},
{AMOVW, C_LOREG, C_NONE, C_REG, 22, 4, 0, 0, C_XPRE},
{AMOVH, C_LOREG, C_NONE, C_REG, 22, 4, 0, 0, C_XPRE},
{AMOVB, C_LOREG, C_NONE, C_REG, 22, 4, 0, 0, C_XPRE},
{AMOVBU, C_LOREG, C_NONE, C_REG, 22, 4, 0, 0, C_XPRE},
{AFMOVS, C_LOREG, C_NONE, C_FREG, 22, 4, 0, 0, C_XPRE},
{AFMOVD, C_LOREG, C_NONE, C_FREG, 22, 4, 0, 0, C_XPRE},
/* pre/post-indexed store (unscaled, signed 9-bit offset) */
{AMOVD, C_REG, C_NONE, C_LOREG, 23, 4, 0, 0, C_XPOST},
{AMOVW, C_REG, C_NONE, C_LOREG, 23, 4, 0, 0, C_XPOST},
{AMOVH, C_REG, C_NONE, C_LOREG, 23, 4, 0, 0, C_XPOST},
{AMOVB, C_REG, C_NONE, C_LOREG, 23, 4, 0, 0, C_XPOST},
{AMOVBU, C_REG, C_NONE, C_LOREG, 23, 4, 0, 0, C_XPOST},
{AFMOVS, C_FREG, C_NONE, C_LOREG, 23, 4, 0, 0, C_XPOST},
{AFMOVD, C_FREG, C_NONE, C_LOREG, 23, 4, 0, 0, C_XPOST},
{AMOVD, C_REG, C_NONE, C_LOREG, 23, 4, 0, 0, C_XPRE},
{AMOVW, C_REG, C_NONE, C_LOREG, 23, 4, 0, 0, C_XPRE},
{AMOVH, C_REG, C_NONE, C_LOREG, 23, 4, 0, 0, C_XPRE},
{AMOVB, C_REG, C_NONE, C_LOREG, 23, 4, 0, 0, C_XPRE},
{AMOVBU, C_REG, C_NONE, C_LOREG, 23, 4, 0, 0, C_XPRE},
{AFMOVS, C_FREG, C_NONE, C_LOREG, 23, 4, 0, 0, C_XPRE},
{AFMOVD, C_FREG, C_NONE, C_LOREG, 23, 4, 0, 0, C_XPRE},
/* pre/post-indexed load/store register pair
(unscaled, signed 10-bit quad-aligned offset) */
{ALDP, C_LOREG, C_NONE, C_PAIR, 66, 4, 0, 0, C_XPRE},
{ALDP, C_LOREG, C_NONE, C_PAIR, 66, 4, 0, 0, C_XPOST},
{ASTP, C_PAIR, C_NONE, C_LOREG, 67, 4, 0, 0, C_XPRE},
{ASTP, C_PAIR, C_NONE, C_LOREG, 67, 4, 0, 0, C_XPOST},
/* special */
{AMOVD, C_SPR, C_NONE, C_REG, 35, 4, 0, 0, 0},
{AMRS, C_SPR, C_NONE, C_REG, 35, 4, 0, 0, 0},
{AMOVD, C_REG, C_NONE, C_SPR, 36, 4, 0, 0, 0},
{AMSR, C_REG, C_NONE, C_SPR, 36, 4, 0, 0, 0},
{AMOVD, C_VCON, C_NONE, C_SPR, 37, 4, 0, 0, 0},
{AMSR, C_VCON, C_NONE, C_SPR, 37, 4, 0, 0, 0},
{AERET, C_NONE, C_NONE, C_NONE, 41, 4, 0, 0, 0},
{AFMOVS, C_FREG, C_NONE, C_UAUTO16K, 20, 4, REGSP, 0, 0},
{AFMOVS, C_FREG, C_NONE, C_NSAUTO, 20, 4, REGSP, 0, 0},
{AFMOVS, C_FREG, C_NONE, C_ZOREG, 20, 4, 0, 0, 0},
{AFMOVS, C_FREG, C_NONE, C_UOREG16K, 20, 4, 0, 0, 0},
{AFMOVS, C_FREG, C_NONE, C_NSOREG, 20, 4, 0, 0, 0},
{AFMOVD, C_FREG, C_NONE, C_UAUTO32K, 20, 4, REGSP, 0, 0},
{AFMOVD, C_FREG, C_NONE, C_NSAUTO, 20, 4, REGSP, 0, 0},
{AFMOVD, C_FREG, C_NONE, C_ZOREG, 20, 4, 0, 0, 0},
{AFMOVD, C_FREG, C_NONE, C_UOREG32K, 20, 4, 0, 0, 0},
{AFMOVD, C_FREG, C_NONE, C_NSOREG, 20, 4, 0, 0, 0},
{AFMOVS, C_UAUTO16K, C_NONE, C_FREG, 21, 4, REGSP, 0, 0},
{AFMOVS, C_NSAUTO, C_NONE, C_FREG, 21, 4, REGSP, 0, 0},
{AFMOVS, C_ZOREG, C_NONE, C_FREG, 21, 4, 0, 0, 0},
{AFMOVS, C_UOREG16K, C_NONE, C_FREG, 21, 4, 0, 0, 0},
{AFMOVS, C_NSOREG, C_NONE, C_FREG, 21, 4, 0, 0, 0},
{AFMOVD, C_UAUTO32K, C_NONE, C_FREG, 21, 4, REGSP, 0, 0},
{AFMOVD, C_NSAUTO, C_NONE, C_FREG, 21, 4, REGSP, 0, 0},
{AFMOVD, C_ZOREG, C_NONE, C_FREG, 21, 4, 0, 0, 0},
{AFMOVD, C_UOREG32K, C_NONE, C_FREG, 21, 4, 0, 0, 0},
{AFMOVD, C_NSOREG, C_NONE, C_FREG, 21, 4, 0, 0, 0},
{AFMOVS, C_FREG, C_NONE, C_LAUTO, 30, 8, REGSP, LTO, 0},
{AFMOVS, C_FREG, C_NONE, C_LOREG, 30, 8, 0, LTO, 0},
{AFMOVD, C_FREG, C_NONE, C_LAUTO, 30, 8, REGSP, LTO, 0},
{AFMOVD, C_FREG, C_NONE, C_LOREG, 30, 8, 0, LTO, 0},
{AFMOVS, C_LAUTO, C_NONE, C_FREG, 31, 8, REGSP, LFROM, 0},
{AFMOVS, C_LOREG, C_NONE, C_FREG, 31, 8, 0, LFROM, 0},
{AFMOVD, C_LAUTO, C_NONE, C_FREG, 31, 8, REGSP, LFROM, 0},
{AFMOVD, C_LOREG, C_NONE, C_FREG, 31, 8, 0, LFROM, 0},
{AFMOVS, C_FREG, C_NONE, C_ADDR, 64, 12, 0, 0, 0},
{AFMOVS, C_ADDR, C_NONE, C_FREG, 65, 12, 0, 0, 0},
{AFMOVD, C_FREG, C_NONE, C_ADDR, 64, 12, 0, 0, 0},
{AFMOVD, C_ADDR, C_NONE, C_FREG, 65, 12, 0, 0, 0},
{AFADDS, C_FREG, C_NONE, C_FREG, 54, 4, 0, 0, 0},
{AFADDS, C_FREG, C_FREG, C_FREG, 54, 4, 0, 0, 0},
{AFADDS, C_FCON, C_NONE, C_FREG, 54, 4, 0, 0, 0},
{AFADDS, C_FCON, C_FREG, C_FREG, 54, 4, 0, 0, 0},
{AFMOVS, C_FCON, C_NONE, C_FREG, 54, 4, 0, 0, 0},
{AFMOVS, C_FREG, C_NONE, C_FREG, 54, 4, 0, 0, 0},
{AFMOVD, C_FCON, C_NONE, C_FREG, 54, 4, 0, 0, 0},
{AFMOVD, C_FREG, C_NONE, C_FREG, 54, 4, 0, 0, 0},
{AFCVTZSD, C_FREG, C_NONE, C_REG, 29, 4, 0, 0, 0},
{ASCVTFD, C_REG, C_NONE, C_FREG, 29, 4, 0, 0, 0},
{AFCMPS, C_FREG, C_FREG, C_NONE, 56, 4, 0, 0, 0},
{AFCMPS, C_FCON, C_FREG, C_NONE, 56, 4, 0, 0, 0},
{AFCCMPS, C_COND, C_REG, C_VCON, 57, 4, 0, 0, 0},
{AFCSELD, C_COND, C_REG, C_FREG, 18, 4, 0, 0, 0},
{AFCVTSD, C_FREG, C_NONE, C_FREG, 29, 4, 0, 0, 0},
{ACASE, C_REG, C_NONE, C_REG, 62, 4 * 4, 0, 0, 0},
{ABCASE, C_NONE, C_NONE, C_SBRA, 63, 4, 0, 0, 0},
{ACLREX, C_NONE, C_NONE, C_VCON, 38, 4, 0, 0, 0},
{ACLREX, C_NONE, C_NONE, C_NONE, 38, 4, 0, 0, 0},
{ACBZ, C_REG, C_NONE, C_SBRA, 39, 4, 0, 0, 0},
{ATBZ, C_VCON, C_REG, C_SBRA, 40, 4, 0, 0, 0},
{ASYS, C_VCON, C_NONE, C_NONE, 50, 4, 0, 0, 0},
{ASYS, C_VCON, C_REG, C_NONE, 50, 4, 0, 0, 0},
{ASYSL, C_VCON, C_NONE, C_REG, 50, 4, 0, 0, 0},
{ADMB, C_VCON, C_NONE, C_NONE, 51, 4, 0, 0, 0},
{AHINT, C_VCON, C_NONE, C_NONE, 52, 4, 0, 0, 0},
{ALDAR, C_ZOREG, C_NONE, C_REG, 58, 4, 0, 0, 0},
{ALDXR, C_ZOREG, C_NONE, C_REG, 58, 4, 0, 0, 0},
{ALDAXR, C_ZOREG, C_NONE, C_REG, 58, 4, 0, 0, 0},
{ALDXP, C_ZOREG, C_REG, C_REG, 58, 4, 0, 0, 0},
{ASTLR, C_REG, C_NONE, C_ZOREG, 59, 4, 0, 0, 0}, // to3=C_NONE
{ASTXR, C_REG, C_NONE, C_ZOREG, 59, 4, 0, 0, 0}, // to3=C_REG
{ASTLXR, C_REG, C_NONE, C_ZOREG, 59, 4, 0, 0, 0}, // to3=C_REG
// { ASTXP, C_REG, C_NONE, C_ZOREG, 59, 4, 0 , 0}, // TODO(aram):
{AAESD, C_VREG, C_NONE, C_VREG, 29, 4, 0, 0, 0},
{ASHA1C, C_VREG, C_REG, C_VREG, 1, 4, 0, 0, 0},
{obj.AUNDEF, C_NONE, C_NONE, C_NONE, 90, 4, 0, 0, 0},
{obj.AUSEFIELD, C_ADDR, C_NONE, C_NONE, 0, 0, 0, 0, 0},
{obj.APCDATA, C_VCON, C_NONE, C_VCON, 0, 0, 0, 0, 0},
{obj.AFUNCDATA, C_VCON, C_NONE, C_ADDR, 0, 0, 0, 0, 0},
{obj.ANOP, C_NONE, C_NONE, C_NONE, 0, 0, 0, 0, 0},
{obj.ADUFFZERO, C_NONE, C_NONE, C_SBRA, 5, 4, 0, 0, 0}, // same as AB/ABL
{obj.ADUFFCOPY, C_NONE, C_NONE, C_SBRA, 5, 4, 0, 0, 0}, // same as AB/ABL
{obj.AXXX, C_NONE, C_NONE, C_NONE, 0, 4, 0, 0, 0},
}
/*
* valid pstate field values, and value to use in instruction
*/
var pstatefield = []struct {
a uint32
b uint32
}{
{REG_SPSel, 0<<16 | 4<<12 | 5<<5},
{REG_DAIFSet, 3<<16 | 4<<12 | 6<<5},
{REG_DAIFClr, 3<<16 | 4<<12 | 7<<5},
}
var pool struct {
start uint32
size uint32
}
func prasm(p *obj.Prog) {
fmt.Printf("%v\n", p)
}
func span7(ctxt *obj.Link, cursym *obj.LSym) {
p := cursym.Text
if p == nil || p.Link == nil { // handle external functions and ELF section symbols
return
}
ctxt.Cursym = cursym
ctxt.Autosize = int32(p.To.Offset&0xffffffff) + 8
if oprange[AAND].start == nil {
buildop(ctxt)
}
bflag := 0
c := int32(0)
p.Pc = int64(c)
var m int
var o *Optab
for p = p.Link; p != nil; p = p.Link {
ctxt.Curp = p
if p.As == ADWORD && (c&7) != 0 {
c += 4
}
p.Pc = int64(c)
o = oplook(ctxt, p)
m = int(o.size)
if m == 0 {
if p.As != obj.ANOP && p.As != obj.AFUNCDATA && p.As != obj.APCDATA {
ctxt.Diag("zero-width instruction\n%v", p)
}
continue
}
switch o.flag & (LFROM | LTO) {
case LFROM:
addpool(ctxt, p, &p.From)
case LTO:
addpool(ctxt, p, &p.To)
break
}
if p.As == AB || p.As == obj.ARET || p.As == AERET { /* TODO: other unconditional operations */
checkpool(ctxt, p, 0)
}
c += int32(m)
if ctxt.Blitrl != nil {
checkpool(ctxt, p, 1)
}
}
cursym.Size = int64(c)
/*
* if any procedure is large enough to
* generate a large SBRA branch, then
* generate extra passes putting branches
* around jmps to fix. this is rare.
*/
for bflag != 0 {
bflag = 0
c = 0
for p = cursym.Text; p != nil; p = p.Link {
if p.As == ADWORD && (c&7) != 0 {
c += 4
}
p.Pc = int64(c)
o = oplook(ctxt, p)
/* very large branches
if(o->type == 6 && p->cond) {
otxt = p->cond->pc - c;
if(otxt < 0)
otxt = -otxt;
if(otxt >= (1L<<17) - 10) {
q = ctxt->arch->prg();
q->link = p->link;
p->link = q;
q->as = AB;
q->to.type = obj.TYPE_BRANCH;
q->cond = p->cond;
p->cond = q;
q = ctxt->arch->prg();
q->link = p->link;
p->link = q;
q->as = AB;
q->to.type = obj.TYPE_BRANCH;
q->cond = q->link->link;
bflag = 1;
}
}
*/
m = int(o.size)
if m == 0 {
if p.As != obj.ANOP && p.As != obj.AFUNCDATA && p.As != obj.APCDATA {
ctxt.Diag("zero-width instruction\n%v", p)
}
continue
}
c += int32(m)
}
}
c += -c & (FuncAlign - 1)
cursym.Size = int64(c)
/*
* lay out the code, emitting code and data relocations.
*/
if ctxt.Tlsg == nil {
ctxt.Tlsg = obj.Linklookup(ctxt, "runtime.tlsg", 0)
}
obj.Symgrow(ctxt, cursym, cursym.Size)
bp := cursym.P
psz := int32(0)
var i int
var out [6]uint32
for p := cursym.Text.Link; p != nil; p = p.Link {
ctxt.Pc = p.Pc
ctxt.Curp = p
o = oplook(ctxt, p)
// need to align DWORDs on 8-byte boundary. The ISA doesn't
// require it, but the various 64-bit loads we generate assume it.
if o.as == ADWORD && psz%8 != 0 {
bp[3] = 0
bp[2] = bp[3]
bp[1] = bp[2]
bp[0] = bp[1]
bp = bp[4:]
psz += 4
}
if int(o.size) > 4*len(out) {
log.Fatalf("out array in span7 is too small, need at least %d for %v", o.size/4, p)
}
asmout(ctxt, p, o, out[:])
for i = 0; i < int(o.size/4); i++ {
ctxt.Arch.ByteOrder.PutUint32(bp, out[i])
bp = bp[4:]
psz += 4
}
}
}
/*
* when the first reference to the literal pool threatens
* to go out of range of a 1Mb PC-relative offset
* drop the pool now, and branch round it.
*/
func checkpool(ctxt *obj.Link, p *obj.Prog, skip int) {
if pool.size >= 0xffff0 || !(ispcdisp(int32(p.Pc+4+int64(pool.size)-int64(pool.start)+8)) != 0) {
flushpool(ctxt, p, skip)
} else if p.Link == nil {
flushpool(ctxt, p, 2)
}
}
func flushpool(ctxt *obj.Link, p *obj.Prog, skip int) {
if ctxt.Blitrl != nil {
if skip != 0 {
if ctxt.Debugvlog != 0 && skip == 1 {
fmt.Printf("note: flush literal pool at %#x: len=%d ref=%x\n", uint64(p.Pc+4), pool.size, pool.start)
}
q := ctxt.NewProg()
q.As = AB
q.To.Type = obj.TYPE_BRANCH
q.Pcond = p.Link
q.Link = ctxt.Blitrl
q.Lineno = p.Lineno
ctxt.Blitrl = q
} else if p.Pc+int64(pool.size)-int64(pool.start) < 1024*1024 {
return
}
// The line number for constant pool entries doesn't really matter.
// We set it to the line number of the preceding instruction so that
// there are no deltas to encode in the pc-line tables.
for q := ctxt.Blitrl; q != nil; q = q.Link {
q.Lineno = p.Lineno
}
ctxt.Elitrl.Link = p.Link
p.Link = ctxt.Blitrl
ctxt.Blitrl = nil /* BUG: should refer back to values until out-of-range */
ctxt.Elitrl = nil
pool.size = 0
pool.start = 0
}
}
/*
* TODO: hash
*/
func addpool(ctxt *obj.Link, p *obj.Prog, a *obj.Addr) {
c := aclass(ctxt, a)
t := *ctxt.NewProg()
t.As = AWORD
sz := 4
// MOVW foo(SB), R is actually
// MOV addr, REGTEMP
// MOVW REGTEMP, R
// where addr is the address of the DWORD containing the address of foo.
if p.As == AMOVD || c == C_ADDR || c == C_VCON {
t.As = ADWORD
sz = 8
}
switch c {
// TODO(aram): remove.
default:
if a.Name != obj.NAME_EXTERN {
fmt.Printf("addpool: %v in %v shouldn't go to default case\n", DRconv(c), p)
}
t.To.Offset = a.Offset
t.To.Sym = a.Sym
t.To.Type = a.Type
t.To.Name = a.Name
/* This is here to work around a bug where we generate negative
operands that match C_MOVCON, but we use them with
instructions that only accept unsigned immediates. This
will cause oplook to return a variant of the instruction
that loads the negative constant from memory, rather than
using the immediate form. Because of that load, we get here,
so we need to know what to do with C_MOVCON.
The correct fix is to use the "negation" instruction variant,
e.g. CMN $1, R instead of CMP $-1, R, or SUB $1, R instead
of ADD $-1, R. */
case C_MOVCON,
/* This is here because MOV uint12<<12, R is disabled in optab.
Because of this, we need to load the constant from memory. */
C_ADDCON,
/* These are here because they are disabled in optab.
Because of this, we need to load the constant from memory. */
C_BITCON,
C_ABCON,
C_MBCON,
C_PSAUTO,
C_PPAUTO,
C_UAUTO4K,
C_UAUTO8K,
C_UAUTO16K,
C_UAUTO32K,
C_UAUTO64K,
C_NSAUTO,
C_NPAUTO,
C_LAUTO,
C_PPOREG,
C_PSOREG,
C_UOREG4K,
C_UOREG8K,
C_UOREG16K,
C_UOREG32K,
C_UOREG64K,
C_NSOREG,
C_NPOREG,
C_LOREG,
C_LACON,
C_LCON,
C_VCON:
if a.Name == obj.NAME_EXTERN {
fmt.Printf("addpool: %v in %v needs reloc\n", DRconv(c), p)
}
t.To.Type = obj.TYPE_CONST
t.To.Offset = ctxt.Instoffset
break
}
for q := ctxt.Blitrl; q != nil; q = q.Link { /* could hash on t.t0.offset */
if q.To == t.To {
p.Pcond = q
return
}
}
q := ctxt.NewProg()
*q = t
q.Pc = int64(pool.size)
if ctxt.Blitrl == nil {
ctxt.Blitrl = q
pool.start = uint32(p.Pc)
} else {
ctxt.Elitrl.Link = q
}
ctxt.Elitrl = q
pool.size = -pool.size & (FuncAlign - 1)
pool.size += uint32(sz)
p.Pcond = q
}
func regoff(ctxt *obj.Link, a *obj.Addr) uint32 {
ctxt.Instoffset = 0
aclass(ctxt, a)
return uint32(ctxt.Instoffset)
}
func ispcdisp(v int32) int {
/* pc-relative addressing will reach? */
return obj.Bool2int(v >= -0xfffff && v <= 0xfffff && (v&3) == 0)
}
func isaddcon(v int64) int {
/* uimm12 or uimm24? */
if v < 0 {
return 0
}
if (v & 0xFFF) == 0 {
v >>= 12
}
return obj.Bool2int(v <= 0xFFF)
}
func isbitcon(v uint64) int {
/* fancy bimm32 or bimm64? */
// TODO(aram):
return 0
// return obj.Bool2int(findmask(v) != nil || (v>>32) == 0 && findmask(v|(v<<32)) != nil)
}
func autoclass(l int64) int {
if l < 0 {
if l >= -256 {
return C_NSAUTO
}
if l >= -512 && (l&7) == 0 {
return C_NPAUTO
}
return C_LAUTO
}
if l <= 255 {
return C_PSAUTO
}
if l <= 504 && (l&7) == 0 {
return C_PPAUTO
}
if l <= 4095 {
return C_UAUTO4K
}
if l <= 8190 && (l&1) == 0 {
return C_UAUTO8K
}
if l <= 16380 && (l&3) == 0 {
return C_UAUTO16K
}
if l <= 32760 && (l&7) == 0 {
return C_UAUTO32K
}
if l <= 65520 && (l&0xF) == 0 {
return C_UAUTO64K
}
return C_LAUTO
}
func oregclass(l int64) int {
if l == 0 {
return C_ZOREG
}
return autoclass(l) - C_NPAUTO + C_NPOREG
}
/*
* given an offset v and a class c (see above)
* return the offset value to use in the instruction,
* scaled if necessary
*/
func offsetshift(ctxt *obj.Link, v int64, c int) int64 {
s := 0
if c >= C_SEXT1 && c <= C_SEXT16 {
s = c - C_SEXT1
} else if c >= C_UAUTO4K && c <= C_UAUTO64K {
s = c - C_UAUTO4K
} else if c >= C_UOREG4K && c <= C_UOREG64K {
s = c - C_UOREG4K
}
vs := v >> uint(s)
if vs<<uint(s) != v {
ctxt.Diag("odd offset: %d\n%v", v, ctxt.Curp)
}
return vs
}
/*
* if v contains a single 16-bit value aligned
* on a 16-bit field, and thus suitable for movk/movn,
* return the field index 0 to 3; otherwise return -1
*/
func movcon(v int64) int {
for s := 0; s < 64; s += 16 {
if (uint64(v) &^ (uint64(0xFFFF) << uint(s))) == 0 {
return s / 16
}
}
return -1
}
func rclass(r int16) int {
switch {
case REG_R0 <= r && r <= REG_R30: // not 31
return C_REG
case r == REGZERO:
return C_ZCON
case REG_F0 <= r && r <= REG_F31:
return C_FREG
case REG_V0 <= r && r <= REG_V31:
return C_VREG
case COND_EQ <= r && r <= COND_NV:
return C_COND
case r == REGSP:
return C_RSP
case r®_EXT != 0:
return C_EXTREG
case r >= REG_SPECIAL:
return C_SPR
}
return C_GOK
}
func aclass(ctxt *obj.Link, a *obj.Addr) int {
switch a.Type {
case obj.TYPE_NONE:
return C_NONE
case obj.TYPE_REG:
return rclass(a.Reg)
case obj.TYPE_REGREG:
return C_PAIR
case obj.TYPE_SHIFT:
return C_SHIFT
case obj.TYPE_MEM:
switch a.Name {
case obj.NAME_EXTERN,
obj.NAME_STATIC:
if a.Sym == nil {
break
}
ctxt.Instoffset = a.Offset
if a.Sym != nil { // use relocation
return C_ADDR
}
return C_LEXT
case obj.NAME_AUTO:
ctxt.Instoffset = int64(ctxt.Autosize) + a.Offset
return autoclass(ctxt.Instoffset)
case obj.NAME_PARAM:
ctxt.Instoffset = int64(ctxt.Autosize) + a.Offset + 8
return autoclass(ctxt.Instoffset)
case obj.TYPE_NONE:
ctxt.Instoffset = a.Offset
return oregclass(ctxt.Instoffset)
}
return C_GOK
case obj.TYPE_FCONST:
return C_FCON
case obj.TYPE_TEXTSIZE:
return C_TEXTSIZE