Synchronize DiSlord's 1.0.70 code.

Completing the NanoVNA-H4 files, now you can compile the NanoVNA-H4 firmware directly using the master branch.

.project

@@ -1,6 +1,6 @@
 <?xml version="1.0" encoding="UTF-8"?>
 <projectDescription>
-	<name>NanoVNA-D</name>
+	<name>NanoVNA-H</name>
 	<comment></comment>
 	<projects>
 	</projects>

Makefile

@@ -7,7 +7,7 @@
 ifeq ($(TARGET),)
   TARGET = F072
 endif
-TARGET=F303
+#TARGET=F303
 
 # Compiler options here.
 ifeq ($(USE_OPT),)

NANOVNA_STM32_F072/adc.c

@@ -0,0 +1,186 @@
+/*
+ * Copyright (c) 2019-2021, Dmitry (DiSlord) dislordlive@gmail.com
+ * Based on TAKAHASHI Tomohiro (TTRFTECH) edy555@gmail.com
+ * All rights reserved.
+ *
+ * This is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 3, or (at your option)
+ * any later version.
+ *
+ * The software is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with GNU Radio; see the file COPYING.  If not, write to
+ * the Free Software Foundation, Inc., 51 Franklin Street,
+ * Boston, MA 02110-1301, USA.
+ */
+
+#define ADC_TR(low, high)               (((uint32_t)(high) << 16U) |        \
+                                         (uint32_t)(low))
+#define ADC_SMPR_SMP_1P5        0U  /**< @brief 14 cycles conversion time   */
+#define ADC_SMPR_SMP_239P5      7U  /**< @brief 252 cycles conversion time. */ 
+#define ADC_CFGR1_RES_12BIT             (0U << 3U)
+
+// External Event Select for regular group
+#define ADC_TIM1_TRGO  0                                       // 0b000
+#define ADC_TIM1_CC4   (ADC_CFGR1_EXTSEL_0)                    // 0b001
+#define ADC_TIM2_TRGO  (ADC_CFGR1_EXTSEL_1)                    // 0b010
+#define ADC_TIM3_TRGO  (ADC_CFGR1_EXTSEL_1|ADC_CFGR1_EXTSEL_0) // 0b011
+#define ADC_TIM15_TRGO (ADC_CFGR1_EXTSEL_2)                    // 0b100
+
+#define VNA_ADC     ADC1
+
+void adc_init(void)
+{
+  rccEnableADC1(FALSE);
+
+  /* Ensure flag states */
+  VNA_ADC->IER = 0;
+
+  /* Calibration procedure.*/
+  ADC->CCR = 0;
+  if (VNA_ADC->CR & ADC_CR_ADEN) {
+    VNA_ADC->CR |= ~ADC_CR_ADDIS; /* Disable ADC */
+  }
+  while (VNA_ADC->CR & ADC_CR_ADEN)
+    ;
+  VNA_ADC->CFGR1 &= ~ADC_CFGR1_DMAEN;
+  VNA_ADC->CR |= ADC_CR_ADCAL;
+  while (VNA_ADC->CR & ADC_CR_ADCAL)
+    ;
+
+  if (VNA_ADC->ISR & ADC_ISR_ADRDY) {
+    VNA_ADC->ISR |= ADC_ISR_ADRDY; /* clear ADRDY */
+  }
+  /* Enable ADC */
+  VNA_ADC->CR |= ADC_CR_ADEN;
+  while (!(VNA_ADC->ISR & ADC_ISR_ADRDY))
+    ;
+}
+
+uint16_t adc_single_read(uint32_t chsel)
+{
+  /* ADC setup */
+  VNA_ADC->ISR    = VNA_ADC->ISR;
+  VNA_ADC->IER    = 0;
+  VNA_ADC->TR     = ADC_TR(0, 0);
+  VNA_ADC->SMPR   = ADC_SMPR_SMP_239P5;
+  VNA_ADC->CFGR1  = ADC_CFGR1_RES_12BIT;
+  VNA_ADC->CHSELR = chsel;
+
+  VNA_ADC->CR |= ADC_CR_ADSTART; // ADC conversion start
+  while (VNA_ADC->CR & ADC_CR_ADSTART)
+    ;
+
+  return VNA_ADC->DR;
+}
+
+int16_t adc_vbat_read(void)
+{
+// Vbat measure averange count = 2^VBAT_AVERAGE
+#define VBAT_AVERAGE 4
+  static int16_t   vbat_raw = 0;
+  static systime_t vbat_time = -VBAT_MEASURE_INTERVAL-1;
+  systime_t _time = chVTGetSystemTimeX();
+  if (_time - vbat_time < VBAT_MEASURE_INTERVAL)
+    goto return_cached;
+  vbat_time = _time;
+// 13.9 Temperature sensor and internal reference voltage
+// VREFINT_CAL calibrated on 3.3V, need get value in mV
+#define ADC_FULL_SCALE 3300
+#define VREFINT_CAL (*((uint16_t*)0x1FFFF7BA))
+  uint32_t vrefint = 0;
+  uint32_t vbat = 0;
+
+  uint8_t restart_touch = 0;
+  if (VNA_ADC->CR & ADC_CR_ADSTART){
+    adc_stop_analog_watchdog();
+    restart_touch = 1;
+  }
+  ADC->CCR |= ADC_CCR_VREFEN | ADC_CCR_VBATEN;
+  for (uint16_t i = 0; i < 1<<VBAT_AVERAGE; i++){
+    // VREFINT == ADC_IN17
+    vrefint+= adc_single_read(ADC_CHSELR_CHSEL17);
+    // VBAT == ADC_IN18
+    // VBATEN enables resiter devider circuit. It consume vbat power.
+    vbat+= adc_single_read(ADC_CHSELR_CHSEL18);
+  }
+  vbat>>=VBAT_AVERAGE;
+  vrefint>>=VBAT_AVERAGE;
+  ADC->CCR &= ~(ADC_CCR_VREFEN | ADC_CCR_VBATEN);
+
+  if (restart_touch)
+    adc_start_analog_watchdog();
+
+  // vbat_raw = (3300 * 2 * vbat / 4095) * (VREFINT_CAL / vrefint)
+  // uint16_t vbat_raw = (ADC_FULL_SCALE * VREFINT_CAL * (float)vbat * 2 / (vrefint * ((1<<12)-1)));
+  // For speed divide not on 4095, divide on 4096, get little error, but no matter
+  vbat_raw = ((ADC_FULL_SCALE * 2 * vbat)>>12) * VREFINT_CAL / vrefint;
+return_cached:
+  if (vbat_raw < 100) {
+    // maybe D2 is not installed
+    return -1;
+  }
+  return vbat_raw + config._vbat_offset;
+}
+
+void adc_start_analog_watchdog(void)
+{
+  // ADC setup, if it is defined a callback for the analog watch dog then it is enabled.
+  VNA_ADC->ISR    = VNA_ADC->ISR;
+  VNA_ADC->IER    = ADC_IER_AWDIE;
+  VNA_ADC->TR     = ADC_TR(0, TOUCH_THRESHOLD);
+  VNA_ADC->SMPR   = ADC_SMPR_SMP_1P5;
+  VNA_ADC->CHSELR = ADC_TOUCH_Y;
+
+  /* ADC configuration and start.*/
+  VNA_ADC->CFGR1  = ADC_CFGR1_RES_12BIT | ADC_CFGR1_AWDEN
+                  | ADC_CFGR1_EXTEN_0 // rising edge of external trigger
+                  | ADC_TIM3_TRGO; // External trigger is timer TIM3
+  /* ADC conversion start.*/
+  VNA_ADC->CR |= ADC_CR_ADSTART;
+}
+
+void adc_stop_analog_watchdog(void)
+{
+  if (VNA_ADC->CR & ADC_CR_ADEN) {
+    if (VNA_ADC->CR & ADC_CR_ADSTART) {
+      VNA_ADC->CR |= ADC_CR_ADSTP;
+      while (VNA_ADC->CR & ADC_CR_ADSTP)
+        ;
+    }
+
+    /*    VNA_ADC->CR |= ADC_CR_ADDIS;
+    while (VNA_ADC->CR & ADC_CR_ADDIS)
+    ;*/
+  }
+}
+
+static void adc_interrupt(void)
+{
+  uint32_t isr = VNA_ADC->ISR;
+  VNA_ADC->ISR = isr;
+
+  if (isr & ADC_ISR_OVR) {
+    /* ADC overflow condition, this could happen only if the DMA is unable
+       to read data fast enough.*/
+
+  }
+  if (isr & ADC_ISR_AWD) {
+    /* Analog watchdog error.*/
+    handle_touch_interrupt();
+  }
+}
+
+OSAL_IRQ_HANDLER(STM32_ADC1_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  adc_interrupt();
+
+  OSAL_IRQ_EPILOGUE();
+}

NANOVNA_STM32_F072/board/stm32f0discovery.cfg

@@ -0,0 +1,11 @@
+# This is an STM32F0 discovery board with a single STM32F051R8T6 chip.
+# http://www.st.com/internet/evalboard/product/253215.jsp
+
+source [find interface/stlink.cfg]
+
+transport select hla_swd
+
+set WORKAREASIZE 0x2000
+source [find target/stm32f0x.cfg]
+
+reset_config srst_only

NANOVNA_STM32_F072/board/stm32f3discovery.cfg

@@ -0,0 +1,12 @@
+# This is an STM32F3 discovery board with a single STM32F303VCT6 chip.
+# http://www.st.com/internet/evalboard/product/254044.jsp
+
+source [find interface/stlink.cfg]
+
+transport select hla_swd
+
+source [find target/stm32f3x.cfg]
+
+#reset_config srst_only
+reset_config none
+

NANOVNA_STM32_F072/debug/STM32F3xx-ADC (OpenOCD, Flash and Run).launch

@@ -0,0 +1,52 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="org.eclipse.cdt.debug.gdbjtag.launchConfigurationType">
+<stringAttribute key="bad_container_name" value="\STM32F3xx-ADC\debug"/>
+<intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.delay" value="1"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.doHalt" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.doReset" value="true"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.initCommands" value="set remotetimeout 20&#13;&#10;monitor reset init&#13;&#10;monitor sleep 50&#13;&#10;"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.jtagDevice" value="Generic TCP/IP"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadImage" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadSymbols" value="true"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.pcRegister" value=""/>
+<intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.portNumber" value="3333"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.runCommands" value=""/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setPcRegister" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setResume" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setStopAt" value="true"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.stopAt" value="main"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsFileName" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsOffset" value=""/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForImage" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForSymbols" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForImage" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForSymbols" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useRemoteTarget" value="true"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.DEBUG_NAME" value="arm-none-eabi-gdb"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.commandFactory" value="Standard"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.protocol" value="mi"/>
+<booleanAttribute key="org.eclipse.cdt.debug.mi.core.verboseMode" value="false"/>
+<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="arm-none-eabi-gdb"/>
+<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/>
+<stringAttribute key="org.eclipse.cdt.launch.COREFILE_PATH" value=""/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_REGISTER_GROUPS" value=""/>
+<stringAttribute key="org.eclipse.cdt.launch.FORMAT" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&lt;contentList/&gt;"/>
+<stringAttribute key="org.eclipse.cdt.launch.GLOBAL_VARIABLES" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;globalVariableList/&gt;&#13;&#10;"/>
+<stringAttribute key="org.eclipse.cdt.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;memoryBlockExpressionList/&gt;&#13;&#10;"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="./build/ch.elf"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="STM32F3xx-ADC"/>
+<booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="true"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value="0.1093754934"/>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+<listEntry value="/STM32F3xx-ADC"/>
+</listAttribute>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+<listEntry value="4"/>
+</listAttribute>
+<listAttribute key="org.eclipse.debug.ui.favoriteGroups">
+<listEntry value="org.eclipse.debug.ui.launchGroup.debug"/>
+</listAttribute>
+</launchConfiguration>

NANOVNA_STM32_F072/interface/stlink.cfg

@@ -0,0 +1,17 @@
+#
+# STMicroelectronics ST-LINK/V1, ST-LINK/V2, ST-LINK/V2-1, STLINK-V3 in-circuit
+# debugger/programmer
+#
+
+interface hla
+hla_layout stlink
+hla_device_desc "ST-LINK"
+hla_vid_pid 0x0483 0x3744 0x0483 0x3748 0x0483 0x374b 0x0483 0x374d 0x0483 0x374e 0x0483 0x374f 0x0483 0x3752 0x0483 0x3753
+
+# Optionally specify the serial number of ST-LINK/V2 usb device.  ST-LINK/V2
+# devices seem to have serial numbers with unreadable characters.  ST-LINK/V2
+# firmware version >= V2.J21.S4 recommended to avoid issues with adapter serial
+# number reset issues.
+# eg.
+#hla_serial "\xaa\xbc\x6e\x06\x50\x75\xff\x55\x17\x42\x19\x3f"
+

NANOVNA_STM32_F072/run_openocd

@@ -0,0 +1 @@
+~/opt/xPacks/@gnu-mcu-eclipse/openocd/0.10.0-12.1/.content/bin/openocd -f board/stm32f0discovery.cfg

NANOVNA_STM32_F072/target/stm32f0x.cfg

@@ -0,0 +1,95 @@
+# script for stm32f0x family
+
+#
+# stm32 devices support SWD transports only.
+#
+source [find target/swj-dp.tcl]
+source [find mem_helper.tcl]
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME stm32f0x
+}
+
+set _ENDIAN little
+
+# Work-area is a space in RAM used for flash programming
+# By default use 4kB
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x1000
+}
+
+# Allow overriding the Flash bank size
+if { [info exists FLASH_SIZE] } {
+	set _FLASH_SIZE $FLASH_SIZE
+} else {
+	# autodetect size
+	set _FLASH_SIZE 0
+}
+
+#jtag scan chain
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+  # See STM Document RM0091
+  # Section 29.5.3
+   set _CPUTAPID 0x0bb11477
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+# flash size will be probed
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME stm32f1x 0x08000000 $_FLASH_SIZE 0 0 $_TARGETNAME
+
+# adapter speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz
+adapter_khz 1000
+
+adapter_nsrst_delay 100
+
+reset_config srst_nogate
+
+if {![using_hla]} {
+   # if srst is not fitted use SYSRESETREQ to
+   # perform a soft reset
+   cortex_m reset_config sysresetreq
+}
+
+proc stm32f0x_default_reset_start {} {
+	# Reset clock is HSI (8 MHz)
+	adapter_khz 1000
+}
+
+proc stm32f0x_default_examine_end {} {
+	# Enable debug during low power modes (uses more power)
+	mmw 0x40015804 0x00000006 0 ;# DBGMCU_CR |= DBG_STANDBY | DBG_STOP
+
+	# Stop watchdog counters during halt
+	mmw 0x40015808 0x00001800 0 ;# DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
+}
+
+proc stm32f0x_default_reset_init {} {
+	# Configure PLL to boost clock to HSI x 6 (48 MHz)
+	mww 0x40021004 0x00100000   ;# RCC_CFGR = PLLMUL[2]
+	mmw 0x40021000 0x01000000 0 ;# RCC_CR[31:16] |= PLLON
+	mww 0x40022000 0x00000011   ;# FLASH_ACR = PRFTBE | LATENCY[0]
+	sleep 10                    ;# Wait for PLL to lock
+	mmw 0x40021004 0x00000002 0 ;# RCC_CFGR |= SW[1]
+
+	# Boost JTAG frequency
+	adapter_khz 8000
+}
+
+# Default hooks
+$_TARGETNAME configure -event examine-end { stm32f0x_default_examine_end }
+$_TARGETNAME configure -event reset-start { stm32f0x_default_reset_start }
+$_TARGETNAME configure -event reset-init { stm32f0x_default_reset_init }