Fix RISCV arch detection (#790)

* Add RISCV alias so arch can be determined by ELF
* Add ptrsize property to RISCV arch
* Allow riscv tests to run

gef.py

@@ -2306,7 +2306,7 @@ def mprotect_asm(cls, addr: int, size: int, perm: Permission) -> str:
 class RISCV(Architecture):
     arch = "RISCV"
     mode = "RISCV"
-    aliases = ("RISCV",)
+    aliases = ("RISCV", Elf.Abi.RISCV)
 
     all_registers = ["$zero", "$ra", "$sp", "$gp", "$tp", "$t0", "$t1",
                      "$t2", "$fp", "$s1", "$a0", "$a1", "$a2", "$a3",
@@ -2345,6 +2345,15 @@ def is_ret(self, insn: Instruction) -> bool:
     def mprotect_asm(cls, addr: int, size: int, perm: Permission) -> str:
         raise OSError(f"Architecture {cls.arch} not supported yet")
 
+    @property
+    def ptrsize(self) -> int:
+        if self._ptrsize is not None:
+            return self._ptrsize
+        if is_alive():
+            self._ptrsize = gdb.parse_and_eval("$pc").type.sizeof
+            return self._ptrsize
+        return 4
+
     def is_conditional_branch(self, insn: Instruction) -> bool:
         return insn.mnemonic.startswith("b")
 

tests/binaries/utils.h

@@ -37,6 +37,10 @@
 // #elif defined(__sparc) || defined(__sparc64__) || defined(__sparc__)
 // #define DebugBreak() { raise( SIGINT ) ; }
 
+/* RISC V */
+#elif defined(__riscv)
+#define DebugBreak() { raise( SIGINT ) ; }
+
 /* the rest */
 #else
 #error "Unsupported architecture"

tests/helpers.py

@@ -14,7 +14,7 @@
 DEFAULT_CONTEXT = "-code -stack"
 ARCH = (os.getenv("GEF_CI_ARCH") or platform.machine()).lower()
 CI_VALID_ARCHITECTURES_32B = ("i686", "armv7l")
-CI_VALID_ARCHITECTURES_64B = ("x86_64", "aarch64", "mips64el", "ppc64le")
+CI_VALID_ARCHITECTURES_64B = ("x86_64", "aarch64", "mips64el", "ppc64le", "riscv64")
 CI_VALID_ARCHITECTURES = CI_VALID_ARCHITECTURES_64B + CI_VALID_ARCHITECTURES_32B
 COVERAGE_DIR = os.getenv("COVERAGE_DIR", "")