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Riscv/ble #874

Merged
merged 2 commits into from Jul 10, 2022
Merged

Riscv/ble #874

merged 2 commits into from Jul 10, 2022

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wafgo
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@wafgo wafgo commented Jul 7, 2022

Description/Motivation/Screenshots

You can observe an error if debugging the RISC-V Linux Kernel under
QEMU which states after hitting the pseudoinstruction blez s1, OFFSET

[!] Command 'context' failed to execute properly, reason: RISC-V:
Conditional instruction `blez s1, 0xffffffff8017f226 <vfs_reag> not
supported yet

Against which architecture was this tested ?

"Tested" indicates that the PR works and the unit test (i.e. make test) run passes without issue.

  • x86-32
  • x86-64
  • ARM
  • AARCH64
  • MIPS
  • POWERPC
  • SPARC
  • RISC-V

Checklist

  • My PR was done against the dev branch, not main.
  • My code follows the code style of this project.
  • My change includes a change to the documentation, if required.
  • If my change adds new code, adequate tests have been added.
  • I have read and agree to the CONTRIBUTING document.

Wadim Mueller added 2 commits July 6, 2022 16:35
You can observe an error if debugging the RISC-V Linux Kernel under
QEMU which states after hitting the pseudoinstruction blez s1, _OFFSET_

[!] Command 'context' failed to execute properly, reason: RISC-V:
Conditional instruction `blez s1, 0xffffffff8017f226 <vfs_reag> not
supported yet

This patches fixes the problem
@hugsy hugsy merged commit 4d4e801 into hugsy:dev Jul 10, 2022
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2 participants