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Fixes
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Give Not found if
l3_cache < 0
l3_assoc < 0
l3_cacheline < 0

Add to Assoc -way

Fix Clock by ic.
cpu_clock_by_ic(200, 0)
replace to:
cpu_clock_by_ic(25, 16)
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@eloaders
eloaders committed Aug 19, 2014
1 parent 0237833 commit 99e382e
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Showing 3 changed files with 46 additions and 27 deletions.
18 changes: 9 additions & 9 deletions I-Nex/i-nex/.src/Finfosys.class
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Original file line number Diff line number Diff line change
Expand Up @@ -98,16 +98,16 @@ Public Sub Form_Open()
Label206.Text = "CPU Clock Measure: " & DATAT["CPU_CLOCK_MEASURE"]
Label207.Text = "Mark TSC: " & DATAT["MARK_TSC"]
Label208.Text = "Mark SYS Clock: " & DATAT["MARK_SYS_CLOCK"]
Label209.Text = "L1 Data: " & DATAT["L1_DATA_CACHE"]
Label210.Text = "L1 Instr: " & DATAT["L1_INSTRUCTION_CACHE"]
Label209.Text = "L1 D: " & DATAT["L1_DATA_CACHE"]
Label210.Text = "L1 I: " & DATAT["L1_INSTRUCTION_CACHE"]
Label211.Text = "L2 Cache: " & DATAT["L2_CACHE"]
Label212.Text = "L3 Cache: " & DATAT["L3_CACHE"]
Label213.Text = "L1 Assoc: " & DATAT["L1_ASSOC"]
Label214.Text = "L2 Assoc: " & DATAT["L2_ASSOC"]
Label215.Text = "L3 Assoc: " & DATAT["L3_ASSOC"]
Label216.Text = "L1 Cacheline: " & DATAT["L1_CACHELINE"]
Label217.Text = "L2 Cacheline: " & DATAT["L2_CACHELINE"]
Label218.Text = "L3 Cacheline: " & DATAT["L3_CACHELINE"]
Label216.Text = "L1 line: " & DATAT["L1_CACHELINE"]
Label217.Text = "L2 line: " & DATAT["L2_CACHELINE"]
Label218.Text = "L3 line: " & DATAT["L3_CACHELINE"]
Label219.Text = "SSE Size: " & DATAT["SSE_SIZE"]

Logs("Create Labels ToolButtons TextLabels in ScrollView1", Logger.Info)
Expand All @@ -123,7 +123,7 @@ Public Sub Form_Open()
Endif
With Label[i]
.X = 2
.Y = 285 + Int(i * 20)
.Y = 310 + Int(i * 20)
.Width = 440
.Height = 21
.Border = Border.Raised
Expand All @@ -137,7 +137,7 @@ Public Sub Form_Open()
End With
With ToolButton[i]
.X = 420
.Y = 285 + Int(i * 20)
.Y = 310 + Int(i * 20)
.Width = 21
.Height = 21
.Picture = YESNO
Expand All @@ -148,7 +148,7 @@ Public Sub Form_Open()
End With
With Button[i]
.X = 400
.Y = 285 + Int(i * 20)
.Y = 310 + Int(i * 20)
.Width = 21
.Height = 21
.Font.Bold = True
Expand All @@ -161,7 +161,7 @@ Public Sub Form_Open()
End With
With TextLabel[i]
.X = 320
.Y = 285 + Int(i * 20)
.Y = 310 + Int(i * 20)
.Width = 80
.Height = 21
.Font.Bold = True
Expand Down
5 changes: 3 additions & 2 deletions I-Nex/i-nex/.src/Finfosys.form
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Original file line number Diff line number Diff line change
Expand Up @@ -584,7 +584,7 @@
Border = Border.Raised
}
{ Separator12 Separator
Move(0,294,441,14)
Move(0,315,441,14)
}
{ Label209 Label
Move(0,210,147,21)
Expand Down Expand Up @@ -657,10 +657,11 @@
Border = Border.Raised
}
{ Label219 Label
Move(147,273,294,21)
Move(0,294,441,21)
Font = Font["Bold,8"]
Padding = 3
Text = ("Label219")
Alignment = Align.Center
Border = Border.Raised
}
}
Expand Down
50 changes: 34 additions & 16 deletions JSON/i-nex-cpuid.c
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Original file line number Diff line number Diff line change
Expand Up @@ -24,7 +24,7 @@ int main(void)
printf("Sorry, your CPU doesn't support CPUID!\n");
return -1;
}
struct cpu_raw_data_t raw; // contains only raw data
struct cpu_raw_data_t raw;
struct cpu_id_t data; // contains recognized CPU features data
if (cpuid_get_raw_data(&raw) < 0) { // obtain the raw CPUID data
printf("Sorry, cannot get the CPUID raw data.\n");
Expand All @@ -51,10 +51,10 @@ int main(void)
printf(" \"STEPPING\": \"%d\",\n", data.stepping); //
printf(" \"EXT_FAMILY\": \"%d\",\n", data.ext_family); //
printf(" \"EXT_MODEL\": \"%d\",\n", data.ext_model); //
printf(" \"CPU_CLOCK\": \"%d\",\n", cpu_clock()); //
printf(" \"CPU_CLOCK_BY_OS\": \"%d\",\n", cpu_clock_by_os()); //
printf(" \"CPU_CLOCK_BY_IC\": \"%d\",\n", cpu_clock_by_ic(200, 0)); //
printf(" \"CPU_CLOCK_MEASURE\": \"%d\",\n", cpu_clock_measure(200, 0));//
printf(" \"CPU_CLOCK\": \"%d MHz\",\n", cpu_clock()); //
printf(" \"CPU_CLOCK_BY_OS\": \"%d MHz\",\n", cpu_clock_by_os()); //
printf(" \"CPU_CLOCK_BY_IC\": \"%d MHz\",\n", cpu_clock_by_ic(25, 16)); //
printf(" \"CPU_CLOCK_MEASURE\": \"%d MHz\",\n", cpu_clock_measure(400, 1));//
printf(" \"MARK_TSC\": \"%llu\",\n", mark.tsc); //
printf(" \"MARK_SYS_CLOCK\": \"%llu\",\n", mark.sys_clock); //
printf(" \"Flags\": {\n");
Expand Down Expand Up @@ -898,17 +898,35 @@ int main(void)
}
printf(" }\n");
printf(" },\n");
printf(" \"L1_DATA_CACHE\": \"%d\",\n", data.l1_data_cache);
printf(" \"L1_INSTRUCTION_CACHE\": \"%d\",\n", data.l1_instruction_cache);
printf(" \"L2_CACHE\": \"%d\",\n", data.l2_cache);
printf(" \"L3_CACHE\": \"%d\",\n", data.l3_cache);
printf(" \"L1_ASSOC\": \"%d\",\n", data.l1_assoc);
printf(" \"L2_ASSOC\": \"%d\",\n", data.l2_assoc);
printf(" \"L3_ASSOC\": \"%d\",\n", data.l3_assoc);
printf(" \"L1_CACHELINE\": \"%d\",\n", data.l1_cacheline);
printf(" \"L2_CACHELINE\": \"%d\",\n", data.l2_cacheline);
printf(" \"L3_CACHELINE\": \"%d\",\n", data.l3_cacheline);
printf(" \"SSE_SIZE\": \"%d\"\n", data.sse_size);
printf(" \"L1_DATA_CACHE\": \"%d KB\",\n", data.l1_data_cache);
printf(" \"L1_INSTRUCTION_CACHE\": \"%d KB\",\n", data.l1_instruction_cache);
printf(" \"L2_CACHE\": \"%d KB\",\n", data.l2_cache);

if (data.l3_cache > 0) {
printf(" \"L3_CACHE\": \"%d KB\",\n", data.l3_cache);
} else {
printf(" \"L3_CACHE\": \"Not found\",\n");
}

printf(" \"L1_ASSOC\": \"%d-way\",\n", data.l1_assoc);
printf(" \"L2_ASSOC\": \"%d-way\",\n", data.l2_assoc);

if (data.l3_assoc > 0) {
printf(" \"L3_ASSOC\": \"%d-way\",\n", data.l3_assoc);
} else {
printf(" \"L3_ASSOC\": \"Not found\",\n");
}

printf(" \"L1_CACHELINE\": \"%d bytes\",\n", data.l1_cacheline);
printf(" \"L2_CACHELINE\": \"%d bytes\",\n", data.l2_cacheline);

if (data.l3_cacheline > 0) {
printf(" \"L3_CACHELINE\": \"%d bytes\",\n", data.l3_cacheline);
} else {
printf(" \"L3_CACHELINE\": \"Not found\",\n");
}

printf(" \"SSE_SIZE\": \"%d bits (%s)\"\n", data.sse_size, data.detection_hints[CPU_HINT_SSE_SIZE_AUTH] ? "authoritative" : "non-authoritative");
printf("}\n");
return 0;
}

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