TDC

Time to digital converter implemented on a Cyclone V (DE10-Nano) FPGA.

Contents

Modules folder holds Verilog modules, including Carry Chains, Dynamic PLLs, and Memory.

Projects folder holds Quartus archived project files.

Python folder holds Python scripts for automating logic placement and memory read/write.

References folder holds sources used in creating TDC.

To-Do

MODULES:

Test & debug Dynamic Phase Lock Loop module (Clocks.v).

Finish TDC.v by implementing system to be measured & control logic.

PYTHON:

Finish TDC.py by including automated measurement of Carry Chain regs.