update SV array support

tests/test_trace_reader.py

@@ -0,0 +1,15 @@
+'''Test wal trace readers'''
+import unittest
+
+from wal.core import Wal
+
+class BasicParserTest(unittest.TestCase):
+    '''Test trace readers'''
+
+    def test_sv_arrays(self):
+        '''Test SystemVerilog arrays'''
+        for trace_format in ['vcd', 'fst']:
+            wal = Wal()
+            wal.load(f'tests/traces/array.{trace_format}')
+            self.assertEqual(wal.eval_str('TOP.tb.data<0>'), 2)
+            self.assertEqual(wal.eval_str('TOP.tb.data<1>'), 0)

tests/traces/array.vcd

@@ -0,0 +1,33 @@
+$version Generated by VerilatedVcd $end
+$timescale 1ps $end
+
+ $scope module TOP $end
+  $scope module tb $end
+   $var wire  8 # data[0] [7:0] $end
+   $var wire  8 $ data[1] [7:0] $end
+   $var wire  8 % data[2] [7:0] $end
+   $var wire  8 & data[3] [7:0] $end
+   $var wire  8 ' data[4] [7:0] $end
+   $var wire  8 ( data[5] [7:0] $end
+   $var wire  8 ) data[6] [7:0] $end
+   $var wire  8 * data[7] [7:0] $end
+   $var wire  8 + data[8] [7:0] $end
+   $var wire  8 , data[9] [7:0] $end
+  $upscope $end
+ $upscope $end
+$enddefinitions $end
+
+
+#0
+b00000010 #
+b00000000 $
+b00000000 %
+b00000000 &
+b00000000 '
+b00000000 (
+b00000000 )
+b00000000 *
+b00000000 +
+b00000000 ,
+#10
+b00000100 #

wal/trace/fst.py

@@ -25,9 +25,12 @@ def __init__(self, file, tid, container, from_string=False, keep_signals=None):
         # get mapping from name to tid and remove trailing signal width, ' [31:0]' etc.
         self.references_to_ids = {re.sub(r' *\[\d+:\d+\]', '', k): v for
                                         k, v in self.references_to_ids.items()}
-        # rename grouped signals like reg(0), reg(1) to reg_0, reg_1
+        # rename grouped signals like reg(0), reg(1) to reg<0>, reg<1>
         self.references_to_ids = {
-            re.sub(r'\(([0-9]+)\)', r'_\1', k): v for k, v in self.references_to_ids.items()}
+            re.sub(r'\(([0-9]+)\)', r'<\1>', k): v for k, v in self.references_to_ids.items()}
+        # rename grouped signals like reg[0], reg[1] to reg<0>, reg<1>
+        self.references_to_ids = {
+            re.sub(r'\[([0-9]+)\]', r'<\1>', k): v for k, v in self.references_to_ids.items()}
 
         self.rawsignals = list(self.references_to_ids.keys())
         self.signals = set(self.rawsignals)

wal/trace/vcd.py

@@ -49,9 +49,12 @@ def parse(self, vcddata):
                 id = tokens[i + 3]
                 name = tokens[i + 4]
 
-                # Remove bit width annotations from the name
-                if name.endswith(']'):
-                    name= name.split('[')[0]
+                # Remove array indices width annotations from name([..])
+                for delim in [('[', ']'), ('(', ')')]:
+                    if name.endswith(delim[1]):
+                        split = name.split(delim[0])
+                        addr = split[-1].replace(delim[1], '>')
+                        name = ''.join(split[:-1]) + '<' + addr
 
                 # only append scope. if not in root scope
                 if scope: