Merge pull request #133 from daurnimator/patch-2

Update link to wishbone-utils
im-tomu · Jan 16, 2020 · 5c83e59 · 5c83e59
2 parents 691de19 + 199cf9f
commit 5c83e59
Showing 1 changed file with 12 additions and 12 deletions.
diff --git a/docs/requirements.rst b/docs/requirements.rst
@@ -172,18 +172,18 @@ Ensure it says **(Fomu build)**. Type ``exit`` to quit ``yosys``.
    The `Fomu Toolchain <https://github.com/im-tomu/fomu-toolchain/releases/latest>`__
    consists of the following tools;
 
-   ============================================================= =============================================
-   Tool                                                          Purpose
-   ============================================================= =============================================
-   `yosys <https://github.com/YosysHQ/yosys>`__                  Verilog synthesis
-   `nextpnr-ice40 <https://github.com/YosysHQ/nextpnr>`__        FPGA place-and-route
-   `icestorm <https://github.com/cliffordwolf/icestorm>`__       FPGA bitstream packing
-   `riscv toolchain <https://www.sifive.com/boards/>`__          Compile code for a RISC-V softcore
-   `dfu-util <https://dfu-util.sourceforge.net/>`__              Load a bitstream or code onto Fomu
-   `python <https://python.org/>`__                              Convert Migen/Litex code to Verilog
-   `wishbone-tool <https://github.com/xobs/wishbone-utils/>`__   Interact with Fomu over USB
-   **serial console**                                            Interact with Python over a virtual console
-   ============================================================= =============================================
+   ================================================================ =============================================
+   Tool                                                             Purpose
+   ================================================================ =============================================
+   `yosys <https://github.com/YosysHQ/yosys>`__                     Verilog synthesis
+   `nextpnr-ice40 <https://github.com/YosysHQ/nextpnr>`__           FPGA place-and-route
+   `icestorm <https://github.com/cliffordwolf/icestorm>`__          FPGA bitstream packing
+   `riscv toolchain <https://www.sifive.com/boards/>`__             Compile code for a RISC-V softcore
+   `dfu-util <https://dfu-util.sourceforge.net/>`__                 Load a bitstream or code onto Fomu
+   `python <https://python.org/>`__                                 Convert Migen/Litex code to Verilog
+   `wishbone-utils <https://github.com/litex-hub/wishbone-utils>`__ Interact with Fomu over USB
+   **serial console**                                               Interact with Python over a virtual console
+   ================================================================ =============================================
 
 
 .. _required-hardware: