How to run BFM simulation

Introduction

ZYNQ BFM is made upon AXI BFM, which needs an extra license besides Vivado because it's a Cadence product.

ZYNQ BFM provides APIs on system level so that the testbench can control all ZYNQ AXI ports with simple function calls. Besides, it emulates the OCM and DDR address spaces for PL AXI Masters to access.

For people who'd like to emulate C code execution, BFM is not the answer. The AXI bus is driven by Verilog. The purpose of ZYNQ BFM is to enable the simulation of a ZYNQ system while PS simulation model is not available. It's useful for Custom IP verification.

ZYNQ BFM also has some limitations. Refer DS897 for details.

Resource

ZYNQ BFM Datasheet: DS897

ZYNQ BFM Example Project: AR55345

AXI BFM Product Guide: PG129

Notes

• If ZYNQ BFM is added by IPI, the IPI top level name doesn't need to be added to the testbench instruction level for BFM instances.
• An extra level of "inst" is needed for BFM API instructions

For example, in AR55345's example project, the API instructions are given by

tb.zynq_sys.zynq_bfm.inst.write_data(32'h4000_0100, 128, wr_m_data[0],wrs);

• zynq_sys is the IPI module instance name in tb
• the IPI module name zynq_system is not needed
• zynq_bfm is the ZYNQ BFM Core's instance name
• inst is added additionally