riscv(asm): fix asm_bswap

This is a WIP, archive only.
infiWang · May 28, 2023 · f84d081 · f84d081
1 parent 227f515
commit f84d081
Showing 1 changed file with 19 additions and 19 deletions.
diff --git a/src/lj_asm_riscv64.h b/src/lj_asm_riscv64.h
@@ -1388,46 +1388,46 @@ static void asm_bswap(ASMState *as, IRIns *ir)
     tmp3 = ra_scratch(as, allow), allow = rset_exclude(allow, tmp3);
     tmp4 = ra_scratch(as, allow), allow = rset_exclude(allow, tmp4);
     tmp5 = ra_scratch(as, allow);
-    emit_ds1s2(as, RISCVI_OR, left, left, tmp1);
-    emit_ds1s2(as, RISCVI_OR, left, left, tmp2);
-    emit_ds1s2(as, RISCVI_OR, left, left, tmp3);
-    emit_dsshamt(as, RISCVI_SLLI, left, left, 56);
+    emit_ds1s2(as, RISCVI_OR, dest, dest, tmp2);
+    emit_ds1s2(as, RISCVI_OR, dest, dest, tmp3);
+    emit_ds1s2(as, RISCVI_OR, dest, dest, tmp1);
     emit_dsshamt(as, RISCVI_SLLI, tmp2, tmp2, 40);
-    emit_ds1s2(as, RISCVI_AND, tmp2, left, tmp2);
+    emit_dsshamt(as, RISCVI_SLLI, dest, left, 56);
     emit_ds1s2(as, RISCVI_OR, tmp3, tmp4, tmp3);
+    emit_ds1s2(as, RISCVI_AND, tmp2, left, tmp2);
     emit_dsshamt(as, RISCVI_SLLI, tmp3, tmp3, 32);
-    emit_dsshamt(as, RISCVI_SRLIW, tmp3, left, 24);
     emit_dsshamt(as, RISCVI_SLLI, tmp4, tmp4, 24);
-    emit_ds1s2(as, RISCVI_AND, tmp4, left, tmp4);
+    emit_dsshamt(as, RISCVI_SRLIW, tmp3, left, 24);
     emit_ds1s2(as, RISCVI_OR, tmp1, tmp3, tmp1);
+    emit_ds1s2(as, RISCVI_AND, tmp4, left, tmp4);
     emit_ds1s2(as, RISCVI_OR, tmp3, tmp5, tmp3);
     emit_dsshamt(as, RISCVI_SLLI, tmp5, tmp5, 24);
     emit_dsshamt(as, RISCVI_SRLIW, tmp5, tmp5, 24);
-    emit_dsshamt(as, RISCVI_SRLI, tmp5, left, 8);
     emit_ds1s2(as, RISCVI_AND, tmp3, tmp3, tmp4);
-    emit_du(as, RISCVI_LUI, tmp4, RISCVF_HI(0xff0000));
+    emit_dsshamt(as, RISCVI_SRLI, tmp5, left, 8);
     emit_dsshamt(as, RISCVI_SRLI, tmp3, left, 24);
     emit_ds1s2(as, RISCVI_OR, tmp1, tmp1, tmp3);
-    emit_dsshamt(as, RISCVI_SRLI, tmp3, left, 56);
+    emit_du(as, RISCVI_LUI, tmp4, RISCVF_HI(0xff0000));
     emit_ds1s2(as, RISCVI_AND, tmp1, tmp1, tmp2);
-    emit_dsi(as, RISCVI_ADDIW, tmp2, tmp2, 0xf00);
-    emit_du(as, RISCVI_LUI, tmp2, RISCVF_HI(0x10000));
+    emit_dsshamt(as, RISCVI_SRLI, tmp3, left, 56);
+    emit_dsi(as, RISCVI_ADDI, tmp2, tmp2, RISCVF_LO(0xff00));
+    emit_du(as, RISCVI_LUI, tmp2, RISCVF_HI(0xff00));
     emit_dsshamt(as, RISCVI_SRLI, tmp1, left, 40);
   } else {
     Reg tmp1, tmp2, tmp3;
     tmp1 = ra_scratch(as, allow), allow = rset_exclude(allow, tmp1);
     tmp2 = ra_scratch(as, allow), allow = rset_exclude(allow, tmp2);
     tmp3 = ra_scratch(as, allow);
-    emit_ds1s2(as, RISCVI_OR, left, left, tmp1);
-    emit_ds1s2(as, RISCVI_OR, left, left, tmp2);
-    emit_dsshamt(as, RISCVI_SLLIW, left, left, 24);
+    emit_ds1s2(as, RISCVI_OR, dest, dest, tmp2);
+    emit_ds1s2(as, RISCVI_OR, dest, dest, tmp1);
     emit_dsshamt(as, RISCVI_SLLI, tmp2, tmp2, 8);
-    emit_ds1s2(as, RISCVI_AND, tmp2, left, tmp2);
+    emit_dsshamt(as, RISCVI_SLLIW, dest, left, 24);
     emit_ds1s2(as, RISCVI_OR, tmp1, tmp1, tmp3);
-    emit_dsshamt(as, RISCVI_SLLI, tmp3, left, 24);
+    emit_ds1s2(as, RISCVI_AND, tmp2, left, tmp2);
     emit_ds1s2(as, RISCVI_AND, tmp1, tmp1, tmp2);
-    emit_dsi(as, RISCVI_ADDI, tmp2, tmp2, 0xf00);
-    emit_du(as, RISCVI_LUI, tmp2, RISCVF_HI(0x10000));
+    emit_dsshamt(as, RISCVI_SRLIW, tmp3, left, 24);
+    emit_dsi(as, RISCVI_ADDI, tmp2, tmp2, RISCVF_LO(0xff00));
+    emit_du(as, RISCVI_LUI, tmp2, RISCVF_HI(0xff00));
     emit_dsshamt(as, RISCVI_SRLI, tmp1, left, 8);
   }
 }