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arm64: dts: Add the OV13850 and OV4689 to dts
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Add the two offical friendlyElec cameras to the device tree, while
activating the second instance of the rkisp1 and the mipi_dphy_tx1rx1.
Mostly a copy of what is found on the friendlyElec fork of the rockchip
downstream BSP kernel tree.
Additionally, increase the temperature limits on the CPU.

Signed-off-by: Sebastian Fricke <sebastian.fricke@posteo.net>
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@initBasti
initBasti committed Jan 17, 2021
1 parent 321af22 commit 9a8e594
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Showing 2 changed files with 205 additions and 3 deletions.
161 changes: 161 additions & 0 deletions arch/arm64/boot/dts/rockchip/rk3399-nanopc-t4.dts
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Original file line number Diff line number Diff line change
Expand Up @@ -32,6 +32,54 @@
vin-supply = <&vcc5v0_sys>;
};

ov13850_avdd_2p8v: 2p8v {
compatible = "regulator-fixed";
regulator-name = "ov13850_avdd";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-always-on;
};

ov13850_dovdd_1p8v: 1p8v {
compatible = "regulator-fixed";
regulator-name = "ov13850_dovdd";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};

ov13850_dvdd_1p2v: 1p2v {
compatible = "regulator-fixed";
regulator-name = "ov13850_dvdd";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-always-on;
};

ov4689_avdd_2p8v: 2p8v {
compatible = "regulator-fixed";
regulator-name = "ov4689_avdd";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-always-on;
};

ov4689_dovdd_1p8v: 1p8v {
compatible = "regulator-fixed";
regulator-name = "ov4689_dovdd";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};

ov4689_dvdd_1p2v: 1p2v {
compatible = "regulator-fixed";
regulator-name = "ov4689_dvdd";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-always-on;
};

adc-keys {
compatible = "adc-keys";
io-channels = <&saradc 1>;
Expand Down Expand Up @@ -99,13 +147,126 @@
vpcie3v3-supply = <&vcc3v3_sys>;
};


&i2c1 {
status = "okay";
ov13850p0: ov13850@10 {
compatible = "ovti,ov13850";
status = "okay";
reg = <0x10>;
clocks = <&cru 0x89>;
clock-names = "xvclk";
avdd-supply = <&ov13850_avdd_2p8v>;
dovdd-supply = <&ov13850_dovdd_1p8v>;
dvdd-supply = <&ov13850_dvdd_1p2v>;

reset-gpios = <&gpio2 27 0>;
pwdn-gpios = <&gpio2 28 0>;
pinctrl-names = "rockchip,camera_default", "rockchip,camera_sleep";
pinctrl-0 = <&cam0_default_pins &cif_clkout_a>;
pinctrl-1 = <&cam0_default_pins>;

port {
ucam_out0b: endpoint {
remote-endpoint = <&mipi_in_ucam0b>;
data-lanes = <1 2>;
};
};
};
};

&i2c2 {
status = "okay";
ov4689p1: ov4689@36 {
compatible = "ovti,ov4689";
status = "okay";
reg = <0x36>;
clocks = <&cru 0x89>;
clock-names = "xvclk";
avdd-supply = <&ov4689_avdd_2p8v>;
dovdd-supply = <&ov4689_dovdd_1p8v>;
dvdd-supply = <&ov4689_dvdd_1p2v>;

reset-gpios = <&gpio2 27 0>;
pwdn-gpios = <&gpio2 28 0>;
pinctrl-names = "rockchip,camera_default", "rockchip,camera_sleep";
pinctrl-0 = <&cam1_default_pins &cif_clkout_a>;
pinctrl-1 = <&cam1_default_pins>;

port {
ucam_out1b: endpoint {
remote-endpoint = <&mipi_in_ucam1b>;
data-lanes = <1 2>;
};
};
};
};

&pinctrl {
ir {
ir_rx: ir-rx {
/* external pullup to VCC3V3_SYS, despite being 1.8V :/ */
rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>;
};
};

cam_pins {
cif_clkout_a: cif-clkout-a {
rockchip,pins = <2 11 3 &pcfg_pull_none>;
};

cif_clkout_a_sleep: cif-clkout-a-sleep {
rockchip,pins = <2 11 0 &pcfg_pull_none>;
};

cam0_default_pins: cam0-default-pins {
rockchip,pins = <2 28 0 &pcfg_pull_down>, <2 27 0 &pcfg_pull_none>;
};

cam1_default_pins: cam1-default-pins {
rockchip,pins = <0 12 0 &pcfg_pull_down>, <0 8 0 &pcfg_pull_none>;
};
};
};

&mipi_dphy_rx0 {
status = "okay";
};

&mipi_dphy_tx1rx1 {
status = "okay";
};

&isp0_mmu {
status = "okay";
};

&isp0 {
status = "okay";

ports {
port@0 {
mipi_in_ucam0b: endpoint@0 {
reg = <0>;
remote-endpoint = <&ucam_out0b>;
data-lanes = <1 2>;
};
};
};
};

&isp1 {
status = "okay";

ports {
port@0 {
mipi_in_ucam1b: endpoint@0 {
reg = <0>;
remote-endpoint = <&ucam_out1b>;
data-lanes = <1 2>;
};
};
};
};

&sdhci {
Expand Down
47 changes: 44 additions & 3 deletions arch/arm64/boot/dts/rockchip/rk3399.dtsi
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Original file line number Diff line number Diff line change
Expand Up @@ -772,17 +772,17 @@

trips {
cpu_alert0: cpu_alert0 {
temperature = <70000>;
temperature = <85000>;
hysteresis = <2000>;
type = "passive";
};
cpu_alert1: cpu_alert1 {
temperature = <75000>;
temperature = <95000>;
hysteresis = <2000>;
type = "passive";
};
cpu_crit: cpu_crit {
temperature = <95000>;
temperature = <100000>;
hysteresis = <2000>;
type = "critical";
};
Expand Down Expand Up @@ -1752,6 +1752,32 @@
};
};

isp1: isp1@ff920000 {
compatible = "rockchip,rk3399-cif-isp";
reg = <0x0 0xff920000 0x0 0x4000>;
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&cru SCLK_ISP1>,
<&cru ACLK_ISP1_WRAPPER>,
<&cru HCLK_ISP1_WRAPPER>;
clock-names = "isp", "aclk", "hclk";
iommus = <&isp1_mmu>;
phys = <&mipi_dphy_tx1rx1>;
phy-names = "dphy";
power-domains = <&power RK3399_PD_ISP1>;
status = "disabled";

ports {
#address-cells = <1>;
#size-cells = <0>;

port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
};
};
};

isp0_mmu: iommu@ff914000 {
compatible = "rockchip,iommu";
reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>;
Expand Down Expand Up @@ -1897,6 +1923,21 @@
};
};

mipi_dphy_tx1rx1: mipi-dphy-tx1rx1@ff968000 {
compatible = "rockchip,rk3399-mipi-dphy";
reg = <0x0 0xff968000 0x0 0x8000>;
clocks = <&cru SCLK_MIPIDPHY_REF>,
<&cru SCLK_DPHY_TX1RX1_CFG>,
<&cru PCLK_VIO_GRF>,
<&cru PCLK_MIPI_DSI1>;
clock-names = "dphy-ref", "dphy-cfg",
"grf", "pclk_mipi_dsi";
#phy-cells = <0>;
rockchip,grf = <&grf>;
power-domains = <&power RK3399_PD_VIO>;
status = "disabled";
};

edp: edp@ff970000 {
compatible = "rockchip,rk3399-edp";
reg = <0x0 0xff970000 0x0 0x8000>;
Expand Down

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