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drivers: mmc: sdhci-cadence: Add debug option for sdhci-cadence driver.
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Use Kernel config CONFIG_MMC_DEBUG to support dumping PHY and host
controller register configuration for debug.

Signed-off-by: Jayanthi Annadurai <jannadurai@marvell.com>
Signed-off-by: Piyush Malgujar <pmalgujar@marvell.com>
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@jannad-mrvl @intel-lab-lkp
jannad-mrvl authored and intel-lab-lkp committed Dec 19, 2022
1 parent 13502b7 commit 2f50d93
Showing 1 changed file with 100 additions and 0 deletions.
100 changes: 100 additions & 0 deletions drivers/mmc/host/sdhci-cadence.c
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Expand Up @@ -15,6 +15,10 @@

#include "sdhci-pltfm.h"

#ifdef CONFIG_MMC_DEBUG
#define DEBUG_DRV pr_info
#endif

#define SDMCLK_MAX_FREQ 200000000

#define DEFAULT_CMD_DELAY 16
Expand Down Expand Up @@ -115,6 +119,10 @@
#define SDHCI_CDNS_SD6_PHY_DLL_SLAVE_CLK_WR_DELAY GENMASK(15, 8)
#define SDHCI_CDNS_SD6_PHY_DLL_SLAVE_READ_DQS_DELAY GENMASK(7, 0)

#define SDHCI_CDNS_SD6_PHY_DLL_OBS_REG0 0x201C
#define SDHCI_CDNS_SD6_PHY_DLL_OBS_REG1 0x2020
#define SDHCI_CDNS_SD6_PHY_DLL_OBS_REG2 0x2024

#define SDHCI_CDNS_SD6_PHY_CTRL 0x2080
#define SDHCI_CDNS_SD6_PHY_CTRL_PHONY_DQS_TIMING GENMASK(9, 4)

Expand Down Expand Up @@ -969,6 +977,94 @@ static void sdhci_cdns_sd6_calc_phy(struct sdhci_cdns_sd6_phy *phy)
}
}

#ifdef CONFIG_MMC_DEBUG
static void sdhci_cdns_sd6_phy_dump(struct sdhci_cdns_sd6_phy *phy)
{
DEBUG_DRV("PHY Timings\n");
DEBUG_DRV("mode %d t_sdclk %d\n", phy->mode, phy->t_sdclk);

DEBUG_DRV("cp_clk_wr_delay %d\n", phy->settings.cp_clk_wr_delay);
DEBUG_DRV("cp_clk_wrdqs_delay %d\n", phy->settings.cp_clk_wrdqs_delay);
DEBUG_DRV("cp_data_select_oe_end %d\n", phy->settings.cp_data_select_oe_end);
DEBUG_DRV("cp_dll_bypass_mode %d\n", phy->settings.cp_dll_bypass_mode);
DEBUG_DRV("cp_dll_locked_mode %d\n", phy->settings.cp_dll_locked_mode);
DEBUG_DRV("cp_dll_start_point %d\n", phy->settings.cp_dll_start_point);
DEBUG_DRV("cp_io_mask_always_on %d\n", phy->settings.cp_io_mask_always_on);
DEBUG_DRV("cp_io_mask_end %d\n", phy->settings.cp_io_mask_end);
DEBUG_DRV("cp_io_mask_start %d\n", phy->settings.cp_io_mask_start);
DEBUG_DRV("cp_rd_del_sel %d\n", phy->settings.cp_rd_del_sel);
DEBUG_DRV("cp_read_dqs_cmd_delay %d\n", phy->settings.cp_read_dqs_cmd_delay);
DEBUG_DRV("cp_read_dqs_delay %d\n", phy->settings.cp_read_dqs_delay);
DEBUG_DRV("cp_sw_half_cycle_shift %d\n", phy->settings.cp_sw_half_cycle_shift);
DEBUG_DRV("cp_sync_method %d\n", phy->settings.cp_sync_method);
DEBUG_DRV("cp_use_ext_lpbk_dqs %d\n", phy->settings.cp_use_ext_lpbk_dqs);
DEBUG_DRV("cp_use_lpbk_dqs %d\n", phy->settings.cp_use_lpbk_dqs);
DEBUG_DRV("cp_use_phony_dqs %d\n", phy->settings.cp_use_phony_dqs);
DEBUG_DRV("cp_use_phony_dqs_cmd %d\n", phy->settings.cp_use_phony_dqs_cmd);
DEBUG_DRV("sdhc_extended_rd_mode %d\n", phy->settings.sdhc_extended_rd_mode);
DEBUG_DRV("sdhc_extended_wr_mode %d\n", phy->settings.sdhc_extended_wr_mode);

DEBUG_DRV("sdhc_hcsdclkadj %d\n", phy->settings.sdhc_hcsdclkadj);
DEBUG_DRV("sdhc_idelay_val %d\n", phy->settings.sdhc_idelay_val);
DEBUG_DRV("sdhc_rdcmd_en %d\n", phy->settings.sdhc_rdcmd_en);
DEBUG_DRV("sdhc_rddata_en %d\n", phy->settings.sdhc_rddata_en);
DEBUG_DRV("sdhc_rw_compensate %d\n", phy->settings.sdhc_rw_compensate);
DEBUG_DRV("sdhc_sdcfsh %d\n", phy->settings.sdhc_sdcfsh);
DEBUG_DRV("sdhc_sdcfsl %d\n", phy->settings.sdhc_sdcfsl);
DEBUG_DRV("sdhc_wrcmd0_dly %d %d\n",
phy->settings.sdhc_wrcmd0_dly, phy->settings.sdhc_wrcmd0_sdclk_dly);
DEBUG_DRV("sdhc_wrcmd1_dly %d %d\n",
phy->settings.sdhc_wrcmd1_dly, phy->settings.sdhc_wrcmd1_sdclk_dly);
DEBUG_DRV("sdhc_wrdata0_dly %d %d\n",
phy->settings.sdhc_wrdata0_dly, phy->settings.sdhc_wrdata0_sdclk_dly);

DEBUG_DRV("sdhc_wrdata1_dly %d %d\n",
phy->settings.sdhc_wrdata1_dly, phy->settings.sdhc_wrdata1_sdclk_dly);
DEBUG_DRV("hs200_tune_val %d\n", phy->settings.hs200_tune_val);
}

void sdhci_cdns_sd6_dump(struct sdhci_cdns_priv *priv)
{
struct sdhci_cdns_sd6_phy *phy = priv->phy;
int id;

sdhci_cdns_sd6_phy_dump(phy);

DEBUG_DRV("Host controller Register Dump\n");
for (id = 0; id < 14; id++)
DEBUG_DRV("HRS%d 0x%x\n", id, readl(priv->hrs_addr + (id * 4)));

id = 29;
DEBUG_DRV("HRS%d 0x%x\n", id, readl(priv->hrs_addr + (id * 4)));
id = 30;
DEBUG_DRV("HRS%d 0x%x\n", id, readl(priv->hrs_addr + (id * 4)));

for (id = 0; id < 27; id++)
DEBUG_DRV("SRS%d 0x%x\n", id, readl(priv->hrs_addr + 0x200 + (id * 4)));

DEBUG_DRV("SDHCI_CDNS_SD6_PHY_DQS_TIMING 0x%x\n",
sdhci_cdns_sd6_read_phy_reg(priv, SDHCI_CDNS_SD6_PHY_DQS_TIMING));
DEBUG_DRV("SDHCI_CDNS_SD6_PHY_GATE_LPBK 0x%x\n",
sdhci_cdns_sd6_read_phy_reg(priv, SDHCI_CDNS_SD6_PHY_GATE_LPBK));
DEBUG_DRV("SDHCI_CDNS_SD6_PHY_DLL_MASTER 0x%x\n",
sdhci_cdns_sd6_read_phy_reg(priv, SDHCI_CDNS_SD6_PHY_DLL_MASTER));
DEBUG_DRV("SDHCI_CDNS_SD6_PHY_DLL_SLAVE 0x%x\n",
sdhci_cdns_sd6_read_phy_reg(priv, SDHCI_CDNS_SD6_PHY_DLL_SLAVE));
DEBUG_DRV("SDHCI_CDNS_SD6_PHY_CTRL 0x%x\n",
sdhci_cdns_sd6_read_phy_reg(priv, SDHCI_CDNS_SD6_PHY_CTRL));
DEBUG_DRV("SDHCI_CDNS_SD6_PHY_GPIO_CTRL0 0x%x\n",
sdhci_cdns_sd6_read_phy_reg(priv, SDHCI_CDNS_SD6_PHY_GPIO_CTRL0));
DEBUG_DRV("SDHCI_CDNS_SD6_PHY_DQ_TIMING 0x%x\n",
sdhci_cdns_sd6_read_phy_reg(priv, SDHCI_CDNS_SD6_PHY_DQ_TIMING));
DEBUG_DRV("SDHCI_CDNS_SD6_PHY_DLL_OBS_REG0 0x%x\n",
sdhci_cdns_sd6_read_phy_reg(priv, SDHCI_CDNS_SD6_PHY_DLL_OBS_REG0));
DEBUG_DRV("SDHCI_CDNS_SD6_PHY_DLL_OBS_REG1 0x%x\n",
sdhci_cdns_sd6_read_phy_reg(priv, SDHCI_CDNS_SD6_PHY_DLL_OBS_REG1));
DEBUG_DRV("SDHCI_CDNS_SD6_PHY_DLL_OBS_REG2 0x%x\n",
sdhci_cdns_sd6_read_phy_reg(priv, SDHCI_CDNS_SD6_PHY_DLL_OBS_REG2));
}
#endif

static int sdhci_cdns_sd6_get_delay_params(struct device *dev, struct sdhci_cdns_priv *priv)
{
struct sdhci_cdns_sd6_phy *phy = priv->phy;
Expand Down Expand Up @@ -1373,6 +1469,10 @@ static void sdhci_cdns_sd6_set_clock(struct sdhci_host *host,
pr_debug("%s: phy init failed\n", __func__);

sdhci_set_clock(host, clock);

#ifdef CONFIG_MMC_DEBUG
sdhci_cdns_sd6_dump(priv);
#endif
}

static int sdhci_cdns_sd4_phy_probe(struct platform_device *pdev,
Expand Down

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