Skip to content

Commit

Permalink
pinctrl: renesas: Add support for 1.8V/2.5V I/O voltage levels
Browse files Browse the repository at this point in the history 
Currently, the Renesas pin control driver supports pins that can switch
their I/O voltage levels between either 1.8V and 3.3V, or between 2.5V
and 3.3V.  However, some SoCs have pins that can switch between 1.8V and
2.5V.

Add support for this by replacing the separate SH_PFC_PIN_CFG_IO_VOLTAGE
capability and voltage level flags by a 2-bit field, to cover three
possible I/O voltage switching options.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
  • Loading branch information
@geertu @intel-lab-lkp
geertu authored and intel-lab-lkp committed Mar 8, 2023
1 parent 1e0dd33 commit 5139325
Show file tree
Hide file tree
Showing 3 changed files with 19 additions and 20 deletions.
4 changes: 2 additions & 2 deletions drivers/pinctrl/renesas/core.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -1125,9 +1125,9 @@ static void __init sh_pfc_check_info(const struct sh_pfc_soc_info *info)
}
}

if (pin->configs & SH_PFC_PIN_CFG_IO_VOLTAGE) {
if (pin->configs & SH_PFC_PIN_CFG_IO_VOLTAGE_MASK) {
if (!info->ops || !info->ops->pin_to_pocctrl)
sh_pfc_err_once(power, "SH_PFC_PIN_CFG_IO_VOLTAGE flag set but .pin_to_pocctrl() not implemented\n");
sh_pfc_err_once(power, "SH_PFC_PIN_CFG_IO_VOLTAGE set but .pin_to_pocctrl() not implemented\n");
else if (info->ops->pin_to_pocctrl(pin->pin, &x) < 0)
sh_pfc_err("pin %s: SH_PFC_PIN_CFG_IO_VOLTAGE set but invalid pin_to_pocctrl()\n",
pin->name);
Expand Down
22 changes: 12 additions & 10 deletions drivers/pinctrl/renesas/pinctrl.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -580,7 +580,7 @@ static bool sh_pfc_pinconf_validate(struct sh_pfc *pfc, unsigned int _pin,
return pin->configs & SH_PFC_PIN_CFG_DRIVE_STRENGTH;

case PIN_CONFIG_POWER_SOURCE:
return pin->configs & SH_PFC_PIN_CFG_IO_VOLTAGE;
return pin->configs & SH_PFC_PIN_CFG_IO_VOLTAGE_MASK;

default:
return false;
Expand Down Expand Up @@ -633,7 +633,7 @@ static int sh_pfc_pinconf_get(struct pinctrl_dev *pctldev, unsigned _pin,
case PIN_CONFIG_POWER_SOURCE: {
int idx = sh_pfc_get_pin_index(pfc, _pin);
const struct sh_pfc_pin *pin = &pfc->info->pins[idx];
unsigned int lower_voltage;
unsigned int mode, lo, hi;
u32 pocctrl, val;
int bit;

Expand All @@ -646,10 +646,11 @@ static int sh_pfc_pinconf_get(struct pinctrl_dev *pctldev, unsigned _pin,

val = sh_pfc_read(pfc, pocctrl);

lower_voltage = (pin->configs & SH_PFC_PIN_VOLTAGE_25_33) ?
2500 : 1800;
mode = pin->configs & SH_PFC_PIN_CFG_IO_VOLTAGE_MASK;
lo = mode <= SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 ? 1800 : 2500;
hi = mode >= SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 ? 3300 : 2500;

arg = (val & BIT(bit)) ? 3300 : lower_voltage;
arg = (val & BIT(bit)) ? hi : lo;
break;
}

Expand Down Expand Up @@ -705,7 +706,7 @@ static int sh_pfc_pinconf_set(struct pinctrl_dev *pctldev, unsigned _pin,
unsigned int mV = pinconf_to_config_argument(configs[i]);
int idx = sh_pfc_get_pin_index(pfc, _pin);
const struct sh_pfc_pin *pin = &pfc->info->pins[idx];
unsigned int lower_voltage;
unsigned int mode, lo, hi;
u32 pocctrl, val;
int bit;

Expand All @@ -716,15 +717,16 @@ static int sh_pfc_pinconf_set(struct pinctrl_dev *pctldev, unsigned _pin,
if (WARN(bit < 0, "invalid pin %#x", _pin))
return bit;

lower_voltage = (pin->configs & SH_PFC_PIN_VOLTAGE_25_33) ?
2500 : 1800;
mode = pin->configs & SH_PFC_PIN_CFG_IO_VOLTAGE_MASK;
lo = mode <= SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 ? 1800 : 2500;
hi = mode >= SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 ? 3300 : 2500;

if (mV != lower_voltage && mV != 3300)
if (mV != lo && mV != hi)
return -EINVAL;

spin_lock_irqsave(&pfc->lock, flags);
val = sh_pfc_read(pfc, pocctrl);
if (mV == 3300)
if (mV == hi)
val |= BIT(bit);
else
val &= ~BIT(bit);
Expand Down
13 changes: 5 additions & 8 deletions drivers/pinctrl/renesas/sh_pfc.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -29,16 +29,13 @@ enum {
#define SH_PFC_PIN_CFG_PULL_DOWN (1 << 3)
#define SH_PFC_PIN_CFG_PULL_UP_DOWN (SH_PFC_PIN_CFG_PULL_UP | \
SH_PFC_PIN_CFG_PULL_DOWN)
#define SH_PFC_PIN_CFG_IO_VOLTAGE (1 << 4)
#define SH_PFC_PIN_CFG_DRIVE_STRENGTH (1 << 5)

#define SH_PFC_PIN_VOLTAGE_18_33 (0 << 6)
#define SH_PFC_PIN_VOLTAGE_25_33 (1 << 6)
#define SH_PFC_PIN_CFG_IO_VOLTAGE_MASK GENMASK(5, 4)
#define SH_PFC_PIN_CFG_IO_VOLTAGE_18_25 (1 << 4)
#define SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 (2 << 4)
#define SH_PFC_PIN_CFG_IO_VOLTAGE_25_33 (3 << 4)

#define SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 (SH_PFC_PIN_CFG_IO_VOLTAGE | \
SH_PFC_PIN_VOLTAGE_18_33)
#define SH_PFC_PIN_CFG_IO_VOLTAGE_25_33 (SH_PFC_PIN_CFG_IO_VOLTAGE | \
SH_PFC_PIN_VOLTAGE_25_33)
#define SH_PFC_PIN_CFG_DRIVE_STRENGTH (1 << 6)

#define SH_PFC_PIN_CFG_NO_GPIO (1 << 31)

Expand Down

0 comments on commit 5139325

Please sign in to comment.