dt-bindings: firmware: Add arm,errata-management

The Errata Management SMCCC interface allows firmware to advertise whether
the OS is affected by an erratum, or if a higher exception level has
mitigated the issue. This allows properties of the device that are not
discoverable by the OS to be described. e.g. some errata depend on the
behaviour of the interconnect, which is not visible to the OS.

Deployed devices may find it significantly harder to update EL3
firmware than the device tree. Erratum workarounds typically have to
fail safe, and assume the platform is affected putting correctness
above performance.

Instead of adding a device-tree entry for any CPU errata that is
relevant (or not) to the platform, allow the device-tree to describe
firmware's responses for the SMCCC interface. This could be used as
the data source for the firmware interface, or be parsed by the OS if
the firmware interface is missing.

Most errata can be detected from CPU id registers. These mechanisms
are only needed for the rare cases that external knowledge is needed.

Suggested-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: James Morse <james.morse@arm.com>

Documentation/devicetree/bindings/arm/cpus.yaml

@@ -257,6 +257,11 @@ properties:
       List of phandles to idle state nodes supported
       by this cpu (see ./idle-states.yaml).
 
+  arm,erratum-list:
+    $ref: '/schemas/types.yaml#/definitions/phandle'
+    description:
+      Specifies the firmware cpu-erratum-list node associated with this CPU.
+
   capacity-dmips-mhz:
     description:
       u32 value representing CPU capacity (see ../cpu/cpu-capacity.txt) in

Documentation/devicetree/bindings/firmware/arm,errata-management.yaml

@@ -0,0 +1,77 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/firmware/arm,errata-management.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Errata Management Firmware Interface
+
+maintainers:
+  - James Morse <james.morse@arm.com>
+
+description: |+
+  The SMC-CC has an erratum discovery interface that allows the OS to discover
+  whether a particular CPU is affected by a specific erratum when the
+  configurations affected is only known by firmware. See the specification of
+  the same title on developer.arm.com, document DEN0100.
+  Provide the values that should be used by the interface, either to supplement
+  firmware, or override the values firmware provides.
+  Most errata can be detected from CPU id registers. These mechanisms are only
+  needed for the rare cases that external knowledge is needed.
+  The CPU node should hold a phandle that points to the cpu-erratum-list node.
+
+properties:
+  compatible:
+    items:
+      - const: arm,cpu-erratum-list
+
+  arm,erratum-affected:
+    description: Erratum numbers that this CPU is affected by.
+    $ref: /schemas/types.yaml#/definitions/uint32-array
+    minItems: 1
+
+  arm,erratum-not-affected:
+    description: Erratum numbers that this CPU is not affected by.
+    $ref: /schemas/types.yaml#/definitions/uint32-array
+    minItems: 1
+
+  arm,erratum-higher-el-mitigation:
+    description: Erratum numbers that have been mitigated by a higher level
+      of firmware
+    $ref: /schemas/types.yaml#/definitions/uint32-array
+    minItems: 1
+
+required:
+  - compatible
+anyOf:
+  - required:
+    - 'arm,erratum-affected'
+  - required:
+    - 'arm,erratum-not-affected'
+  - required:
+    - 'arm,erratum-higher-el-mitigation'
+
+additionalProperties: false
+
+examples:
+  - |
+    firmware {
+      CL1_ERRATA: cluster1-errata {
+          compatible = "arm,cpu-erratum-list";
+          arm,erratum-not-affected = <2701952>;
+      };
+    };
+
+    cpus {
+      #size-cells = <0>;
+      #address-cells = <1>;
+
+      cpu@0 {
+        device_type = "cpu";
+        compatible = "arm,cortex-x2";
+        reg = <0x0>;
+        arm,erratum-list = <&CL1_ERRATA>;
+      };
+    };
+
+...