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mmc: xenon: Fix 2G limitation on AC5 SoC
There is a limitation on AC5 SoC that mmc controller can't have DMA access over 2G memory, so use SDMA with a bounce buffer. Swiotlb can't help because on arm64 arch it reserves memblock's at the end of the memory. Additionally set mask to 34 bit since on AC5 SoC RAM starts at 0x2_00000000. Co-developed-by: Elad Nachman <enachman@marvell.com> Signed-off-by: Elad Nachman <enachman@marvell.com> Signed-off-by: Vadym Kochan <vadym.kochan@plvision.eu>
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