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Removed old CPUID wrappers
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@AlexAltea
AlexAltea committed Jun 15, 2018
1 parent 63e4a5d commit f25bdda
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Showing 10 changed files with 76 additions and 303 deletions.
13 changes: 10 additions & 3 deletions core/cpu.c
View file
Expand Up @@ -31,6 +31,7 @@
#include "../include/hax.h"
#include "include/ia32.h"
#include "include/cpu.h"
#include "include/cpuid.h"
#include "include/vcpu.h"
#include "include/debug.h"
#include "include/dump_vmcs.h"
Expand All @@ -42,6 +43,12 @@ static vmx_error_t cpu_vmentry_failed(struct vcpu_t *vcpu, vmx_error_t err);
static int cpu_vmexit_handler(struct vcpu_t *vcpu, exit_reason_t exit_reason,
struct hax_tunnel *htun);

static bool cpu_has_feature(uint32_t feature)
{
// TODO: Use cache
return cpuid_has_feature(feature);
}

static int cpu_emt64_enable()
{
uint32 effer;
Expand Down Expand Up @@ -69,17 +76,17 @@ void cpu_init_vmx(void *arg)
cpu_data = current_cpu_data();

cpu_data->cpu_features |= HAX_CPUF_VALID;
if (!cpu_has_vmx_support())
if (!cpu_has_feature(X86_FEATURE_VMX))
return;
else
cpu_data->cpu_features |= HAX_CPUF_SUPPORT_VT;

if (!cpu_has_nx_support())
if (!cpu_has_feature(X86_FEATURE_NX))
return;
else
cpu_data->cpu_features |= HAX_CPUF_SUPPORT_NX;

if(cpu_has_emt64_support())
if (cpu_has_feature(X86_FEATURE_EM64T))
cpu_data->cpu_features |= HAX_CPUF_SUPPORT_EM64T;

nx_enable = cpu_nx_enable();
Expand Down
6 changes: 3 additions & 3 deletions core/cpuid.c
View file
Expand Up @@ -58,7 +58,7 @@ static uint32_t cpuid_query_root(uint32_t eax, uint32_t value_reg)
{
cpuid_args_t args;
args.eax = eax;
__handle_cpuid(&args); // TODO
// __handle_cpuid(&args); // TODO
return args.regs[value_reg];
}

Expand All @@ -68,7 +68,7 @@ static uint32_t cpuid_query_leaf(uint32_t eax, uint32_t value_reg,
cpuid_args_t args;
args.regs[leaf_reg] = leaf_val;
args.eax = eax;
__handle_cpuid(&args); // TODO
// __handle_cpuid(&args); // TODO
return args.regs[value_reg];
}

Expand All @@ -87,7 +87,7 @@ bool cpuid_cache_has_feature(uint32_t* cache, uint32_t feature_key)
cpuid_feature_t feature;
feature.value = feature_key;
if (feature.index >= CPUID_CACHE_SIZE) {
return false;
return cpuid_has_feature(feature_key);
}
if (cache[feature.index] & (1 << feature.value_bit)) {
return true;
Expand Down
1 change: 1 addition & 0 deletions core/haxlib.vcxproj
View file
Expand Up @@ -262,6 +262,7 @@
<ItemGroup>
<!-- We only add items (e.g. form ClSourceFiles) that do not already exist (e.g in the ClCompile list), this avoids duplication -->
<ClCompile Include="@(ClSourceFiles)" Exclude="@(ClCompile)" />
<ClCompile Include="cpuid.c" />
<ResourceCompile Include="@(RcSourceFiles)" Exclude="@(ResourceCompile)" />
<Midl Include="@(IdlSourceFiles)" Exclude="@(Midl)" />
<MessageCompile Include="@(McSourceFiles)" Exclude="@(MessageCompile)" />
Expand Down
2 changes: 2 additions & 0 deletions core/include/cpu.h
View file
Expand Up @@ -169,6 +169,8 @@ void cpu_enter_vmx(void *arg);

void cpu_pmu_init(void *arg);

bool cpu_has_feature(uint32_t feature);

void hax_panic_log(struct vcpu_t *vcpu);
void hax_clear_panic_log(struct vcpu_t *vcpu);

Expand Down
65 changes: 0 additions & 65 deletions core/include/ia32.h
View file
Expand Up @@ -242,71 +242,6 @@ enum {
EXC_SIMD = 19
};

enum {
feat_none = 0U, // 0
feat_fpu = 1U << 0, // 0x1
feat_vme = 1U << 1, // 0x2
feat_de = 1U << 2, // 0x4
feat_pse = 1U << 3, // 0x8
feat_tsc = 1U << 4, // 0x10
feat_msr = 1U << 5, // 0x20
feat_pae = 1U << 6, // 0x40
feat_mce = 1U << 7, // 0x80
feat_cx8 = 1U << 8, // 0x100
feat_apic = 1U << 9, // 0x200
feat_sep = 1U << 11, // 0x800
feat_mtrr = 1U << 12, // 0x1000
feat_pge = 1U << 13, // 0x2000
feat_mca = 1U << 14, // 0x4000
feat_cmov = 1U << 15, // 0x8000
feat_pat = 1U << 16, // 0x10000
feat_pse36 = 1U << 17, // 0x20000
feat_psn = 1U << 18, // 0x40000
feat_clfsh = 1U << 19, // 0x80000
feat_ds = 1U << 21, // 0x200000
feat_acpi = 1U << 22, // 0x400000
feat_mmx = 1U << 23, // 0x800000
feat_fxsr = 1U << 24, // 0x1000000
feat_sse = 1U << 25, // 0x2000000
feat_sse2 = 1U << 26, // 0x4000000
feat_ss = 1U << 27, // 0x8000000
feat_htt = 1U << 28, // 0x10000000
feat_tm = 1U << 29, // 0x20000000
feat_pbe = 1U << 31, // 0x80000000

feat_sse3 = 1U << 0, // 0x1
feat_pclmulqdq = 1U << 1, // 0x2
feat_dtes64 = 1U << 2, // 0x4
feat_monitor = 1U << 3, // 0x8
feat_dscpl = 1U << 4, // 0x10
feat_vmx = 1U << 5, // 0x20
feat_smx = 1U << 6, // 0x40
feat_est = 1U << 7, // 0x80
feat_tm2 = 1U << 8, // 0x100
feat_ssse3 = 1U << 9, // 0x200
feat_cnxtid = 1U << 10, // 0x400
feat_cmpxchg16b = 1U << 13, // 0x2000
feat_xtpr_update = 1U << 14, // 0x4000
feat_pdcm = 1U << 15, // 0x8000
feat_dca = 1U << 18, // 0x40000
feat_sse41 = 1U << 19, // 0x80000
feat_sse42 = 1U << 20, // 0x100000
feat_x2apic = 1U << 21, // 0x200000
feat_movbe = 1U << 22, // 0x400000
feat_popcnt = 1U << 23, // 0x800000
feat_aes = 1U << 25, // 0x2000000
feat_xsave = 1U << 26, // 0x4000000
feat_osxsave = 1U << 27, // 0x8000000
feat_hypervisor = 1U << 31, // 0x80000000

feat_lahf = 1U << 0, // 0x1

feat_syscall = 1U << 11, // 0x800
feat_execute_disable = 1U << 20, // 0x10000
feat_rdtscp = 1U << 27, // 0x8000000
feat_em64t = 1U << 29 // 0x20000000
};

// For IA32_APIC_BASE MSR (see IASDM Vol. 3A 10.4.4)
#define APIC_BASE_BSP (1ULL << 8)
#define APIC_BASE_ENABLE (1ULL << 11)
Expand Down
109 changes: 60 additions & 49 deletions core/vcpu.c
View file
Expand Up @@ -34,6 +34,7 @@
#include "include/mtrr.h"
#include "include/vmx.h"
#include "include/cpu.h"
#include "include/cpuid.h"
#include "include/vm.h"
#include "include/debug.h"
#include "include/dump_vmcs.h"
Expand Down Expand Up @@ -911,10 +912,11 @@ void save_guest_msr(struct vcpu_t *vcpu)
{
int i;
struct gstate *gstate = &vcpu->gstate;
bool em64t_support = cpu_has_feature(X86_FEATURE_EM64T);

for (i = 0; i < NR_GMSR; i++) {
gstate->gmsr[i].entry = gmsr_list[i];
if (cpu_has_emt64_support() || !is_emt64_msr(gmsr_list[i])) {
if (em64t_support || !is_emt64_msr(gmsr_list[i])) {
gstate->gmsr[i].value = ia32_rdmsr(gstate->gmsr[i].entry);
}
}
Expand All @@ -930,17 +932,19 @@ void save_guest_msr(struct vcpu_t *vcpu)
gstate->apm_pes_msrs[i] = ia32_rdmsr(msr);
}

// TODO: Check if host supports RDTSCP
gstate->tsc_aux = ia32_rdmsr(IA32_TSC_AUX);
if (!cpu_has_feature(X86_FEATURE_RDTSCP)) {
gstate->tsc_aux = ia32_rdmsr(IA32_TSC_AUX);
}
}

void load_guest_msr(struct vcpu_t *vcpu)
{
int i;
struct gstate *gstate = &vcpu->gstate;
bool em64t_support = cpu_has_feature(X86_FEATURE_EM64T);

for (i = 0; i < NR_GMSR; i++) {
if (cpu_has_emt64_support() || !is_emt64_msr(gstate->gmsr[i].entry)) {
if (em64t_support || !is_emt64_msr(gstate->gmsr[i].entry)) {
ia32_wrmsr(gstate->gmsr[i].entry, gstate->gmsr[i].value);
}
}
Expand All @@ -956,18 +960,20 @@ void load_guest_msr(struct vcpu_t *vcpu)
ia32_wrmsr(msr, gstate->apm_pes_msrs[i]);
}

// TODO: Check if host supports RDTSCP
ia32_wrmsr(IA32_TSC_AUX, gstate->tsc_aux);
if (!cpu_has_feature(X86_FEATURE_RDTSCP)) {
ia32_wrmsr(IA32_TSC_AUX, gstate->tsc_aux);
}
}

static void save_host_msr(struct vcpu_t *vcpu)
{
int i;
struct hstate *hstate = &get_cpu_data(vcpu->cpu_id)->hstate;
bool em64t_support = cpu_has_feature(X86_FEATURE_EM64T);

for (i = 0; i < NR_HMSR; i++) {
hstate->hmsr[i].entry = hmsr_list[i];
if (cpu_has_emt64_support() || !is_emt64_msr(hmsr_list[i])) {
if (em64t_support || !is_emt64_msr(hmsr_list[i])) {
hstate->hmsr[i].value = ia32_rdmsr(hstate->hmsr[i].entry);
}
}
Expand All @@ -983,17 +989,19 @@ static void save_host_msr(struct vcpu_t *vcpu)
hstate->apm_pes_msrs[i] = ia32_rdmsr(msr);
}

// TODO: Check if host supports RDTSCP
hstate->tsc_aux = ia32_rdmsr(IA32_TSC_AUX);
if (!cpu_has_feature(X86_FEATURE_RDTSCP)) {
hstate->tsc_aux = ia32_rdmsr(IA32_TSC_AUX);
}
}

static void load_host_msr(struct vcpu_t *vcpu)
{
int i;
struct hstate *hstate = &get_cpu_data(vcpu->cpu_id)->hstate;
bool em64t_support = cpu_has_feature(X86_FEATURE_EM64T);

for (i = 0; i < NR_HMSR; i++) {
if (cpu_has_emt64_support() || !is_emt64_msr(hstate->hmsr[i].entry)) {
if (em64t_support || !is_emt64_msr(hstate->hmsr[i].entry)) {
ia32_wrmsr(hstate->hmsr[i].entry, hstate->hmsr[i].value);
}
}
Expand All @@ -1009,8 +1017,9 @@ static void load_host_msr(struct vcpu_t *vcpu)
ia32_wrmsr(msr, hstate->apm_pes_msrs[i]);
}

// TODO: Check if host supports RDTSCP
ia32_wrmsr(IA32_TSC_AUX, hstate->tsc_aux);
if (!cpu_has_feature(X86_FEATURE_RDTSCP)) {
ia32_wrmsr(IA32_TSC_AUX, hstate->tsc_aux);
}
}

void vcpu_save_host_state(struct vcpu_t *vcpu)
Expand Down Expand Up @@ -2314,43 +2323,43 @@ static void handle_cpuid_virtual(struct vcpu_t *vcpu, uint32 a, uint32 c)

static uint32 cpu_features_1 =
// pat is disabled!
feat_fpu |
feat_vme |
feat_de |
feat_tsc |
feat_msr |
feat_pae |
feat_mce |
feat_cx8 |
feat_apic |
feat_sep |
feat_mtrr |
feat_pge |
feat_mca |
feat_cmov |
feat_clfsh |
feat_mmx |
feat_fxsr |
feat_sse |
feat_sse2 |
feat_ss |
feat_pse |
feat_htt;
FEATURE(FPU) |
FEATURE(VME) |
FEATURE(DE) |
FEATURE(TSC) |
FEATURE(MSR) |
FEATURE(PAE) |
FEATURE(MCE) |
FEATURE(CX8) |
FEATURE(APIC) |
FEATURE(SEP) |
FEATURE(MTRR) |
FEATURE(PGE) |
FEATURE(MCA) |
FEATURE(CMOV) |
FEATURE(CLFLUSHOPT) |
FEATURE(MMX) |
FEATURE(FXSR) |
FEATURE(SSE) |
FEATURE(SSE2) |
FEATURE(SS) |
FEATURE(PSE) |
FEATURE(HTT);

static uint32 cpu_features_2 =
feat_sse3 |
feat_ssse3 |
feat_sse41 |
feat_sse42 |
feat_cmpxchg16b |
feat_movbe |
feat_popcnt;
FEATURE(SSE3) |
FEATURE(SSSE3) |
FEATURE(SSE41) |
FEATURE(SSE42) |
FEATURE(CMPXCHG16B) |
FEATURE(MOVBE) |
FEATURE(POPCNT);

uint32 cpu_features_ext =
feat_execute_disable |
feat_syscall |
feat_rdtscp |
feat_em64t;
FEATURE(NX) |
FEATURE(SYSCALL) |
FEATURE(RDTSCP) |
FEATURE(EM64T);

uint8 physical_address_size;

Expand Down Expand Up @@ -2407,7 +2416,7 @@ static void handle_cpuid_virtual(struct vcpu_t *vcpu, uint32 a, uint32 c)
// supported by the host CPU, but including "hypervisor", which is
// desirable for VMMs.
// TBD: This will need to be changed to emulate new features.
state->_ecx = (cpu_features_2 & state->_ecx) | feat_hypervisor;
state->_ecx = (cpu_features_2 & state->_ecx) | FEATURE(HYPERVISOR);
state->_edx = cpu_features_1 & state->_edx;
return;
}
Expand Down Expand Up @@ -3076,7 +3085,10 @@ static int handle_msr_read(struct vcpu_t *vcpu, uint32 msr, uint64 *val)
break;
}
case IA32_TSC_AUX: {
// TODO: Check if host supports RDTSCP
if (!cpu_has_feature(X86_FEATURE_RDTSCP)) {
r = 1;
break;
}
*val = gstate->tsc_aux & 0xFFFFFFFF;
break;
}
Expand Down Expand Up @@ -3344,8 +3356,7 @@ static int handle_msr_write(struct vcpu_t *vcpu, uint32 msr, uint64 val)
break;
}
case IA32_TSC_AUX: {
// TODO: Check if host supports RDTSCP
if (val >> 32) {
if (!cpu_has_feature(X86_FEATURE_RDTSCP) || (val >> 32)) {
r = 1;
break;
}
Expand Down

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