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[Encode] MFX and MI refining for AVC
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* [Encode] MFX and MI refining for AVC

- refine mfx and mi interface for AVC
- unify get cmd size function
- move const value for GPR to mi interface
- move address to mfx interface
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@dmenshov @intel-mediadev
dmenshov authored and intel-mediadev committed Feb 8, 2022
1 parent bfb7cb2 commit 2bfedfc
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Showing 7 changed files with 144 additions and 29 deletions.
2 changes: 1 addition & 1 deletion media_common/agnostic/common/codec/shared/codec_def_common.h
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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2017-2021, Intel Corporation
* Copyright (c) 2017-2022, Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
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28 changes: 14 additions & 14 deletions media_common/agnostic/common/hw/vdbox/mhw_vdbox_huc_def.h
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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2021, Intel Corporation
* Copyright (c) 2021-2022, Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
Expand Down Expand Up @@ -42,21 +42,21 @@ typedef struct _MHW_VDBOX_HUC_REGION_PARAMS
//!
enum CommandsNumberOfAddresses
{
MI_STORE_DATA_IMM_CMD_NUMBER_OF_ADDRESSES = 1, // 2 DW for 1 address field
MI_FLUSH_DW_CMD_NUMBER_OF_ADDRESSES = 1, // 2 DW for 1 address field
MI_CONDITIONAL_BATCH_BUFFER_END_CMD_NUMBER_OF_ADDRESSES = 1, // 2 DW for 1 address field
MI_STORE_REGISTER_MEM_CMD_NUMBER_OF_ADDRESSES = 1, // 2 DW for 1 address field
MI_COPY_MEM_MEM_CMD_NUMBER_OF_ADDRESSES = 2, // 4 DW for 2 address fields
MI_STORE_DATA_IMM_CMD_NUMBER_OF_ADDRESSES = 1, // 2 DW for 1 address field
MI_FLUSH_DW_CMD_NUMBER_OF_ADDRESSES = 1, // 2 DW for 1 address field
MI_CONDITIONAL_BATCH_BUFFER_END_CMD_NUMBER_OF_ADDRESSES = 1, // 2 DW for 1 address field
MI_STORE_REGISTER_MEM_CMD_NUMBER_OF_ADDRESSES = 1, // 2 DW for 1 address field
MI_COPY_MEM_MEM_CMD_NUMBER_OF_ADDRESSES = 2, // 4 DW for 2 address fields

VD_PIPELINE_FLUSH_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for 0 address fields
VD_PIPELINE_FLUSH_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for 0 address fields

HUC_PIPE_MODE_SELECT_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields
HUC_IMEM_STATE_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields
HUC_DMEM_STATE_CMD_NUMBER_OF_ADDRESSES = 2, // 3 DW for 2 address fields
HUC_VIRTUAL_ADDR_STATE_CMD_NUMBER_OF_ADDRESSES = 16, // 32 DW for 16 address fields
HUC_IND_OBJ_BASE_ADDR_STATE_CMD_NUMBER_OF_ADDRESSES = 4, // 8 DW for 4 address fields
HUC_STREAM_OBJECT_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields
HUC_START_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields
HUC_PIPE_MODE_SELECT_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields
HUC_IMEM_STATE_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields
HUC_DMEM_STATE_CMD_NUMBER_OF_ADDRESSES = 2, // 3 DW for 2 address fields
HUC_VIRTUAL_ADDR_STATE_CMD_NUMBER_OF_ADDRESSES = 16, // 32 DW for 16 address fields
HUC_IND_OBJ_BASE_ADDR_STATE_CMD_NUMBER_OF_ADDRESSES = 4, // 8 DW for 4 address fields
HUC_STREAM_OBJECT_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields
HUC_START_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields
};

#endif
9 changes: 9 additions & 0 deletions media_softlet/agnostic/common/hw/mhw_mi_impl.h
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Expand Up @@ -39,6 +39,15 @@ namespace mhw
{
namespace mi
{
static constexpr uint32_t GENERAL_PURPOSE_REGISTER0_LO_OFFSET_NODE_1_INIT = 0x1C0600;
static constexpr uint32_t GENERAL_PURPOSE_REGISTER0_HI_OFFSET_NODE_1_INIT = 0x1C0604;
static constexpr uint32_t GENERAL_PURPOSE_REGISTER4_LO_OFFSET_NODE_1_INIT = 0x1C0620;
static constexpr uint32_t GENERAL_PURPOSE_REGISTER4_HI_OFFSET_NODE_1_INIT = 0x1C0624;
static constexpr uint32_t GENERAL_PURPOSE_REGISTER11_LO_OFFSET_NODE_1_INIT = 0x1C0658;
static constexpr uint32_t GENERAL_PURPOSE_REGISTER11_HI_OFFSET_NODE_1_INIT = 0x1C065C;
static constexpr uint32_t GENERAL_PURPOSE_REGISTER12_LO_OFFSET_NODE_1_INIT = 0x1C0660;
static constexpr uint32_t GENERAL_PURPOSE_REGISTER12_HI_OFFSET_NODE_1_INIT = 0x1C0664;

template <typename cmd_t>
class Impl : public Itf, public mhw::Impl
{
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66 changes: 65 additions & 1 deletion media_softlet/agnostic/common/hw/vdbox/mhw_vdbox_mfx_impl.h
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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2021, Intel Corporation
* Copyright (c) 2021-2022, Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
Expand Down Expand Up @@ -29,6 +29,7 @@

#include "mhw_vdbox_mfx_itf.h"
#include "mhw_impl.h"
#include "mhw_mi_impl.h"

#ifdef IGFX_MFX_INTERFACE_EXT_SUPPORT
#include "mhw_vdbox_mfx_impl_ext.h"
Expand All @@ -48,10 +49,28 @@ namespace vdbox
{
namespace mfx
{
//VDBOX MFX register offsets
static constexpr uint32_t MFC_IMAGE_STATUS_MASK_REG_OFFSET_NODE_1_INIT = 0x1C08B4;
static constexpr uint32_t MFC_IMAGE_STATUS_CTRL_REG_OFFSET_NODE_1_INIT = 0x1C08B8;
static constexpr uint32_t MFC_AVC_NUM_SLICES_REG_OFFSET_NODE_1_INIT = 0x1C0954;
static constexpr uint32_t MFC_QP_STATUS_COUNT_OFFSET_NODE_1_INIT = 0x1C08BC;
static constexpr uint32_t MFX_ERROR_FLAG_REG_OFFSET_NODE_1_INIT = 0x1C0800;
static constexpr uint32_t MFX_FRAME_CRC_REG_OFFSET_NODE_1_INIT = 0x1C0850;
static constexpr uint32_t MFX_MB_COUNT_REG_OFFSET_NODE_1_INIT = 0x1C0868;
static constexpr uint32_t MFC_BITSTREAM_BYTECOUNT_FRAME_REG_OFFSET_NODE_1_INIT = 0x1C08A0;
static constexpr uint32_t MFC_BITSTREAM_SE_BITCOUNT_FRAME_REG_OFFSET_NODE_1_INIT = 0x1C08A4;
static constexpr uint32_t MFC_BITSTREAM_BYTECOUNT_SLICE_REG_OFFSET_NODE_1_INIT = 0x1C08D0;

//VDBOX MFX register initial value
static constexpr uint32_t MFX_LRA0_REG_OFFSET_NODE_1_INIT = 0;
static constexpr uint32_t MFX_LRA1_REG_OFFSET_NODE_1_INIT = 0;
static constexpr uint32_t MFX_LRA2_REG_OFFSET_NODE_1_INIT = 0;

template<typename cmd_t>
class Impl : public Itf, public mhw::Impl
{
_MFX_CMD_DEF(_MHW_CMD_ALL_DEF_FOR_IMPL);
MmioRegistersMfx m_mmioRegisters[MHW_VDBOX_NODE_MAX] = {}; //!< Mfx mmio registers

public:
MOS_STATUS SetCacheabilitySettings(MHW_MEMORY_OBJECT_CONTROL_PARAMS settings[MOS_CODEC_RESOURCE_USAGE_END_CODEC]) override
Expand Down Expand Up @@ -359,6 +378,19 @@ class Impl : public Itf, public mhw::Impl
return eStatus;
}

MmioRegistersMfx *GetMmioRegisters(MHW_VDBOX_NODE_IND index) override
{
if (index < MHW_VDBOX_NODE_MAX)
{
return &m_mmioRegisters[index];
}
else
{
MHW_ASSERT("index is out of range!");
return &m_mmioRegisters[MHW_VDBOX_NODE_1];
}
}

MHW_MEMORY_OBJECT_CONTROL_PARAMS m_preDeblockingMemoryCtrl;
MHW_MEMORY_OBJECT_CONTROL_PARAMS m_postDeblockingMemoryCtrl;
MHW_MEMORY_OBJECT_CONTROL_PARAMS m_OriginalUncompressedPictureSourceMemoryCtrl;
Expand All @@ -378,6 +410,36 @@ class Impl : public Itf, public mhw::Impl
MHW_MEMORY_OBJECT_CONTROL_PARAMS m_bitplaneReadBufferIndexToMemoryCtrl;
MHW_MEMORY_OBJECT_CONTROL_PARAMS m_directMvBufferForWriteCtrl;

private:
void InitMmioRegisters()
{
MmioRegistersMfx *mmioRegisters = &m_mmioRegisters[MHW_VDBOX_NODE_1];

mmioRegisters->generalPurposeRegister0LoOffset = mhw::mi::GENERAL_PURPOSE_REGISTER0_LO_OFFSET_NODE_1_INIT;
mmioRegisters->generalPurposeRegister0HiOffset = mhw::mi::GENERAL_PURPOSE_REGISTER0_HI_OFFSET_NODE_1_INIT;
mmioRegisters->generalPurposeRegister4LoOffset = mhw::mi::GENERAL_PURPOSE_REGISTER4_LO_OFFSET_NODE_1_INIT;
mmioRegisters->generalPurposeRegister4HiOffset = mhw::mi::GENERAL_PURPOSE_REGISTER4_HI_OFFSET_NODE_1_INIT;
mmioRegisters->generalPurposeRegister11LoOffset = mhw::mi::GENERAL_PURPOSE_REGISTER11_LO_OFFSET_NODE_1_INIT;
mmioRegisters->generalPurposeRegister11HiOffset = mhw::mi::GENERAL_PURPOSE_REGISTER11_HI_OFFSET_NODE_1_INIT;
mmioRegisters->generalPurposeRegister12LoOffset = mhw::mi::GENERAL_PURPOSE_REGISTER12_LO_OFFSET_NODE_1_INIT;
mmioRegisters->generalPurposeRegister12HiOffset = mhw::mi::GENERAL_PURPOSE_REGISTER12_HI_OFFSET_NODE_1_INIT;
mmioRegisters->mfcImageStatusMaskRegOffset = MFC_IMAGE_STATUS_MASK_REG_OFFSET_NODE_1_INIT;
mmioRegisters->mfcImageStatusCtrlRegOffset = MFC_IMAGE_STATUS_CTRL_REG_OFFSET_NODE_1_INIT;
mmioRegisters->mfcAvcNumSlicesRegOffset = MFC_AVC_NUM_SLICES_REG_OFFSET_NODE_1_INIT;
mmioRegisters->mfcQPStatusCountOffset = MFC_QP_STATUS_COUNT_OFFSET_NODE_1_INIT;
mmioRegisters->mfxErrorFlagsRegOffset = MFX_ERROR_FLAG_REG_OFFSET_NODE_1_INIT;
mmioRegisters->mfxFrameCrcRegOffset = MFX_FRAME_CRC_REG_OFFSET_NODE_1_INIT;
mmioRegisters->mfxMBCountRegOffset = MFX_MB_COUNT_REG_OFFSET_NODE_1_INIT;
mmioRegisters->mfcBitstreamBytecountFrameRegOffset = MFC_BITSTREAM_BYTECOUNT_FRAME_REG_OFFSET_NODE_1_INIT;
mmioRegisters->mfcBitstreamSeBitcountFrameRegOffset = MFC_BITSTREAM_SE_BITCOUNT_FRAME_REG_OFFSET_NODE_1_INIT;
mmioRegisters->mfcBitstreamBytecountSliceRegOffset = MFC_BITSTREAM_BYTECOUNT_SLICE_REG_OFFSET_NODE_1_INIT;
mmioRegisters->mfxLra0RegOffset = MFX_LRA0_REG_OFFSET_NODE_1_INIT;
mmioRegisters->mfxLra1RegOffset = MFX_LRA1_REG_OFFSET_NODE_1_INIT;
mmioRegisters->mfxLra2RegOffset = MFX_LRA2_REG_OFFSET_NODE_1_INIT;

m_mmioRegisters[MHW_VDBOX_NODE_2] = m_mmioRegisters[MHW_VDBOX_NODE_1];
}

protected:
using base_t = Itf;
MhwCpInterface *m_cpItf = nullptr;
Expand All @@ -387,6 +449,8 @@ class Impl : public Itf, public mhw::Impl
{
MHW_FUNCTION_ENTER;
m_cpItf = cpItf;

InitMmioRegisters();
InitRowstoreUserFeatureSettings();
SetCacheabilitySettings();
}
Expand Down
43 changes: 42 additions & 1 deletion media_softlet/agnostic/common/hw/vdbox/mhw_vdbox_mfx_itf.h
View file
@@ -1,5 +1,5 @@
/*
* Copyright (c) 2021, Intel Corporation
* Copyright (c) 2021-2022, Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
Expand Down Expand Up @@ -77,6 +77,45 @@ namespace mfx
class Itf
{
public:
#define PATCH_LIST_COMMAND(x) (x##_NUMBER_OF_ADDRESSES)
//!
//! \enum CommandsNumberOfAddresses
//! \brief Commands number of addresses
//!
enum CommandsNumberOfAddresses
{
// MFX Engine Commands
MI_BATCH_BUFFER_START_CMD_NUMBER_OF_ADDRESSES = 1, // 2 DW for 1 address field
MFX_PIPE_MODE_SELECT_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields
MFX_SURFACE_STATE_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields
MFX_PIPE_BUF_ADDR_STATE_CMD_NUMBER_OF_ADDRESSES = 27, // 50 DW for 25 address fields, added 2 for DownScaledReconPicAddr
MFX_IND_OBJ_BASE_ADDR_STATE_CMD_NUMBER_OF_ADDRESSES = 5, // 10 DW for 5 address fields
MFX_WAIT_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields
MFX_BSP_BUF_BASE_ADDR_STATE_CMD_NUMBER_OF_ADDRESSES = 3, // 2 DW for 3 address fields
MFD_AVC_PICID_STATE_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields
MFX_AVC_DIRECTMODE_STATE_CMD_NUMBER_OF_ADDRESSES = 17, // 50 DW for 17 address fields
MFX_AVC_IMG_STATE_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields
MFX_QM_STATE_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields
MFX_FQM_STATE_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields
MFD_VC1_LONG_PIC_STATE_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields
MFX_VC1_PRED_PIPE_STATE_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields
MFX_VC1_DIRECTMODE_STATE_CMD_NUMBER_OF_ADDRESSES = 2, // 2 DW for 2 address fields
MFX_MPEG2_PIC_STATE_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields
MFX_DBK_OBJECT_CMD_NUMBER_OF_ADDRESSES = 4, // 2 DW for 4 address fields
MFX_VP8_PIC_STATE_CMD_NUMBER_OF_ADDRESSES = 2, // 2 DW for 2 address fields
MFX_AVC_SLICE_STATE_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields
MFD_AVC_BSD_OBJECT_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields
MFD_AVC_DPB_STATE_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields
MFD_AVC_SLICEADDR_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields
MFX_AVC_REF_IDX_STATE_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields
MFX_AVC_WEIGHTOFFSET_STATE_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields
MFC_AVC_PAK_INSERT_OBJECT_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields
MFD_VC1_BSD_OBJECT_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields
MFD_VC1_IT_OBJECT_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields
MFD_MPEG2_BSD_OBJECT_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields
MFD_MPEG2_IT_OBJECT_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields
MFD_VP8_BSD_OBJECT_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields
};
bool IsVPlanePresent(MOS_FORMAT format)
{
switch (format)
Expand Down Expand Up @@ -225,6 +264,8 @@ class Itf

virtual MOS_STATUS FindGpuNodeToUse(PMHW_VDBOX_GPUNODE_LIMIT gpuNodeLimit) = 0;

virtual MmioRegistersMfx *GetMmioRegisters(MHW_VDBOX_NODE_IND index) = 0;

vdbox::RowStoreCache m_intraRowstoreCache = {}; //!< Intra rowstore cache
vdbox::RowStoreCache m_deblockingFilterRowstoreCache = {}; //!< Deblocking filter row store cache
vdbox::RowStoreCache m_bsdMpcRowstoreCache = {}; //!< BSD/MPC row store cache
Expand Down
22 changes: 11 additions & 11 deletions media_softlet/agnostic/common/media_interfaces/media_interfaces_mhw_next.h
View file
@@ -1,5 +1,5 @@
/*
* Copyright (c) 2021, Intel Corporation
* Copyright (c) 2021-2022, Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
Expand Down Expand Up @@ -98,17 +98,17 @@ class MhwInterfacesNext

//! \brief These interfaces are responsible for constructing instructions,
//! structures, and registers for hardware.
MhwCpInterface *m_cpInterface = nullptr;
MhwMiInterface *m_miInterface = nullptr;
MhwRenderInterface *m_renderInterface = nullptr;
MhwSfcInterface *m_sfcInterface = nullptr;
MhwCpInterface *m_cpInterface = nullptr;
MhwMiInterface *m_miInterface = nullptr;
MhwRenderInterface *m_renderInterface = nullptr;
MhwSfcInterface *m_sfcInterface = nullptr;
XMHW_STATE_HEAP_INTERFACE *m_stateHeapInterface = nullptr;
MhwVeboxInterface *m_veboxInterface = nullptr;
MhwVdboxMfxInterface *m_mfxInterface = nullptr;
MhwVdboxHcpInterface *m_hcpInterface = nullptr;
MhwVdboxHucInterface *m_hucInterface = nullptr;
MhwVdboxVdencInterface *m_vdencInterface = nullptr;
MhwBltInterface *m_bltInterface = nullptr;
MhwVeboxInterface *m_veboxInterface = nullptr;
MhwVdboxMfxInterface *m_mfxInterface = nullptr;
MhwVdboxHcpInterface *m_hcpInterface = nullptr;
MhwVdboxHucInterface *m_hucInterface = nullptr;
MhwVdboxVdencInterface *m_vdencInterface = nullptr;
MhwBltInterface *m_bltInterface = nullptr;

/* New mhw sub interfaces*/
std::shared_ptr<mhw::vdbox::avp::Itf> m_avpItf = nullptr;
Expand Down
3 changes: 2 additions & 1 deletion media_softlet/agnostic/common/shared/mediacontext/media_context.cpp
View file
Expand Up @@ -422,11 +422,12 @@ MOS_STATUS MediaContext::FunctionToNode(MediaFunction func, const MOS_GPUCTX_CRE
MOS_STATUS MediaContext::FunctionToNodeCodec(MOS_GPU_NODE& node)
{
CodechalHwInterface *hwInterface = static_cast<CodechalHwInterface *>(m_hwInterface);
std::shared_ptr<mhw::vdbox::mfx::Itf> mfxItf = hwInterface->GetMfxInterfaceNext();
MhwVdboxMfxInterface *mfxInterface = hwInterface->GetMfxInterface();
MOS_OS_CHK_NULL_RETURN(mfxInterface);

MHW_VDBOX_GPUNODE_LIMIT gpuNodeLimit = {0};
if (hwInterface->GetMfxInterfaceNext())
if (mfxItf)
{
MOS_OS_CHK_STATUS_RETURN(hwInterface->GetMfxInterfaceNext()->FindGpuNodeToUse(&gpuNodeLimit));
}
Expand Down

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