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[MOS] Enable virtual engine for Gen11.
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@zxye
zxye committed Sep 17, 2018
1 parent cc873fa commit f3ee06e
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Showing 9 changed files with 255 additions and 185 deletions.
180 changes: 90 additions & 90 deletions media_driver/linux/common/os/libdrm/include/i915_drm.h
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Original file line number Diff line number Diff line change
Expand Up @@ -74,8 +74,8 @@
* the __user boundary with pointers encapsulated inside u64.
*/
struct i915_user_extension {
__u64 next_extension;
__u64 name;
__u64 next_extension;
__u64 name;
};
/*
* Different engines serve different roles, and there may be more than one
Expand All @@ -85,12 +85,12 @@ struct i915_user_extension {
* information about that group.
*/
enum drm_i915_gem_engine_class {
I915_ENGINE_CLASS_RENDER = 0,
I915_ENGINE_CLASS_COPY = 1,
I915_ENGINE_CLASS_VIDEO = 2,
I915_ENGINE_CLASS_VIDEO_ENHANCE = 3,
I915_ENGINE_CLASS_RENDER = 0,
I915_ENGINE_CLASS_COPY = 1,
I915_ENGINE_CLASS_VIDEO = 2,
I915_ENGINE_CLASS_VIDEO_ENHANCE = 3,

I915_ENGINE_CLASS_INVALID = -1
I915_ENGINE_CLASS_INVALID = -1
};
/* Each region is a minimum of 16k, and there are at most 255 of them.
*/
Expand Down Expand Up @@ -289,7 +289,7 @@ struct drm_i915_cmd_parser_append {
#define DRM_I915_OVERLAY_PUT_IMAGE 0x27
#define DRM_I915_OVERLAY_ATTRS 0x28
#define DRM_I915_GEM_EXECBUFFER2 0x29
#define DRM_I915_GEM_EXECBUFFER2_WR DRM_I915_GEM_EXECBUFFER2
#define DRM_I915_GEM_EXECBUFFER2_WR DRM_I915_GEM_EXECBUFFER2
#define DRM_I915_GET_SPRITE_COLORKEY 0x2a
#define DRM_I915_SET_SPRITE_COLORKEY 0x2b
#define DRM_I915_GEM_WAIT 0x2c
Expand All @@ -302,7 +302,7 @@ struct drm_i915_cmd_parser_append {
#define DRM_I915_GEM_USERPTR 0x33
#define DRM_I915_GEM_CONTEXT_GETPARAM 0x34
#define DRM_I915_GEM_CONTEXT_SETPARAM 0x35
#define DRM_I915_QUERY 0x39
#define DRM_I915_QUERY 0x39
#define DRM_I915_PERFMON 0x3e

#ifndef ANDROID
Expand Down Expand Up @@ -333,7 +333,7 @@ struct drm_i915_cmd_parser_append {
#define DRM_IOCTL_I915_GEM_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init)
#define DRM_IOCTL_I915_GEM_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer)
#define DRM_IOCTL_I915_GEM_EXECBUFFER2 DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2, struct drm_i915_gem_execbuffer2)
#define DRM_IOCTL_I915_GEM_EXECBUFFER2_WR DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2_WR, struct drm_i915_gem_execbuffer2)
#define DRM_IOCTL_I915_GEM_EXECBUFFER2_WR DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2_WR, struct drm_i915_gem_execbuffer2)
#define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin)
#define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin)
#define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy)
Expand All @@ -359,14 +359,14 @@ struct drm_i915_cmd_parser_append {
#define DRM_IOCTL_I915_SET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey)
#define DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey)
#define DRM_IOCTL_I915_GEM_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_WAIT, struct drm_i915_gem_wait)
#define DRM_IOCTL_I915_GEM_CONTEXT_CREATE DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create_v2)
#define DRM_IOCTL_I915_GEM_CONTEXT_CREATE DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create_v2)
#define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy)
#define DRM_IOCTL_I915_REG_READ DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read)
#define DRM_IOCTL_I915_GET_RESET_STATS DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GET_RESET_STATS, struct drm_i915_reset_stats)
#define DRM_IOCTL_I915_GEM_USERPTR DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_USERPTR, struct drm_i915_gem_userptr)
#define DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_GETPARAM, struct drm_i915_gem_context_param)
#define DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_SETPARAM, struct drm_i915_gem_context_param)
#define DRM_IOCTL_I915_QUERY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_QUERY, struct drm_i915_query)
#define DRM_IOCTL_I915_QUERY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_QUERY, struct drm_i915_query)

#ifndef ANDROID
#define DRM_IOCTL_I915_LOAD_BALANCING_HINT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_LOAD_BALANCING_HINT, struct drm_i915_ring_load_query)
Expand Down Expand Up @@ -1321,13 +1321,13 @@ struct drm_i915_gem_context_create {
};

struct drm_i915_gem_context_create_v2 {
/* output: id of new context*/
__u32 ctx_id;
__u32 flags;
#define I915_GEM_CONTEXT_SHARE_GTT 0x1
#define I915_GEM_CONTEXT_SINGLE_TIMELINE 0x2
__u32 share_ctx;
__u32 pad;
/* output: id of new context*/
__u32 ctx_id;
__u32 flags;
#define I915_GEM_CONTEXT_SHARE_GTT 0x1
#define I915_GEM_CONTEXT_SINGLE_TIMELINE 0x2
__u32 share_ctx;
__u32 pad;
};

struct drm_i915_gem_context_destroy {
Expand Down Expand Up @@ -1411,7 +1411,7 @@ struct drm_i915_gem_context_param {
* Extensions:
* i915_context_engines_load_balance (I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE)
*/
#define I915_CONTEXT_PARAM_ENGINES 0x7
#define I915_CONTEXT_PARAM_ENGINES 0x7

__u64 value;
};
Expand All @@ -1431,26 +1431,26 @@ struct drm_i915_gem_context_param {
* The context must be defined to use a single timeline for all engines.
*/
struct i915_context_engines_load_balance {
struct i915_user_extension base;
struct i915_user_extension base;

__u64 flags; /* all undefined flags must be zero */
__u64 engines_mask;
__u64 flags; /* all undefined flags must be zero */
__u64 engines_mask;

__u64 mbz[4]; /* reserved for future use; must be zero */
__u64 mbz[4]; /* reserved for future use; must be zero */
};

struct i915_context_param_engines {
__u64 extensions;
__u64 extensions;
#define I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE 0

struct {
struct {
#ifdef __cplusplus
__u32 engine_class;
__u32 engine_class;
#else
__u32 class; /* see enum drm_i915_gem_engine_class */
__u32 class; /* see enum drm_i915_gem_engine_class */
#endif
__u32 instance;
} class_instance[0];
__u32 instance;
} class_instance[0];
};

struct drm_i915_gem_context_param_sseu {
Expand Down Expand Up @@ -1482,43 +1482,43 @@ typedef struct drm_i915_ring_load_query
} drm_i915_ring_load_query;

struct drm_i915_query_item {
__u64 query_id;
__u64 query_id;
#define DRM_I915_QUERY_TOPOLOGY_INFO 1
#define DRM_I915_QUERY_ENGINE_INFO 2

/*
* When set to zero by userspace, this is filled with the size of the
* data to be written at the data_ptr pointer. The kernel set this
* value to a negative value to signal an error on a particular query
* item.
*/
__s32 length;

/*
* Unused for now.
*/
__u32 flags;

/*
* Data will be written at the location pointed by data_ptr when the
* value of length matches the length of the data to be written by the
* kernel.
*/
__u64 data_ptr;
#define DRM_I915_QUERY_ENGINE_INFO 2

/*
* When set to zero by userspace, this is filled with the size of the
* data to be written at the data_ptr pointer. The kernel set this
* value to a negative value to signal an error on a particular query
* item.
*/
__s32 length;

/*
* Unused for now.
*/
__u32 flags;

/*
* Data will be written at the location pointed by data_ptr when the
* value of length matches the length of the data to be written by the
* kernel.
*/
__u64 data_ptr;
};

struct drm_i915_query {
__u32 num_items;
__u32 num_items;

/*
* Unused for now.
*/
__u32 flags;
/*
* Unused for now.
*/
__u32 flags;

/*
* This point to an array of num_items drm_i915_query_item structures.
*/
__u64 items_ptr;
/*
* This point to an array of num_items drm_i915_query_item structures.
*/
__u64 items_ptr;
};

/**
Expand All @@ -1529,36 +1529,36 @@ struct drm_i915_query {
* capabilities where applicable.
*/
struct drm_i915_engine_info {
/**
* Engine flags.
*
* I915_ENGINE_FLAG_PHYSICAL - engine exists in the hardware
* 915_ENGINE_FLAG_ABI - engine can be submitted to via execbuf
*/
__u64 flags;
#define I915_ENGINE_FLAG_PHYSICAL (1 << 0)
#define I915_ENGINE_FLAG_ABI (1 << 1)

/** Engine class as in enum drm_i915_gem_engine_class. */
/**
* Engine flags.
*
* I915_ENGINE_FLAG_PHYSICAL - engine exists in the hardware
* 915_ENGINE_FLAG_ABI - engine can be submitted to via execbuf
*/
__u64 flags;
#define I915_ENGINE_FLAG_PHYSICAL (1 << 0)
#define I915_ENGINE_FLAG_ABI (1 << 1)

/** Engine class as in enum drm_i915_gem_engine_class. */
#ifdef __cplusplus
__u16 engine_class;
__u16 engine_class;
#else
__u16 class;
__u16 class;
#endif
/** Engine instance number. */
__u16 instance;
/** Engine instance number. */
__u16 instance;

/** Reserved field must be cleared to zero. */
__u32 rsvd0;
/** Reserved field must be cleared to zero. */
__u32 rsvd0;

/** Capabilities of this engine. */
__u64 capabilities;
#define I915_VCS_CLASS_CAPABILITY_HEVC (1 << 0)
#define I915_VCS_CLASS_CAPABILITY_SFC (1 << 1)
/** Capabilities of this engine. */
__u64 capabilities;
#define I915_VCS_CLASS_CAPABILITY_HEVC (1 << 0)
#define I915_VCS_CLASS_CAPABILITY_SFC (1 << 1)
#define I915_VCS_CLASS_CAPABILITY_INVALID 0xFFFFFFFFFFFFFFFF;

/** Reserved fields must be cleared to zero. */
__u64 rsvd1[2];
/** Reserved fields must be cleared to zero. */
__u64 rsvd1[2];
};

/**
Expand All @@ -1568,14 +1568,14 @@ struct drm_i915_engine_info {
* the array of struct drm_i915_engine_info structures.
*/
struct drm_i915_query_engine_info {
/** Number of struct drm_i915_engine_info structs following. */
__u32 num_engines;
/** Number of struct drm_i915_engine_info structs following. */
__u32 num_engines;

/** MBZ */
__u32 rsvd[3];
/** MBZ */
__u32 rsvd[3];

/** Marker for drm_i915_engine_info structures. */
struct drm_i915_engine_info engines[];
/** Marker for drm_i915_engine_info structures. */
struct drm_i915_engine_info engines[];
};

#define MAX_ENGINE_NUM 8
Expand Down
4 changes: 2 additions & 2 deletions media_driver/linux/common/os/libdrm/include/mos_bufmgr.h
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Original file line number Diff line number Diff line change
Expand Up @@ -387,8 +387,8 @@ int mos_get_subslice_total(int fd, unsigned int *subslice_total);
int mos_get_eu_total(int fd, unsigned int *eu_total);

struct class_instance {
uint32_t engine_class;
uint32_t instance;
uint32_t engine_class;
uint32_t instance;
};
int mos_query_engines(int fd,
__u32 engine_class,
Expand Down
7 changes: 6 additions & 1 deletion media_driver/linux/common/os/mos_context_specific.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -552,7 +552,12 @@ MOS_STATUS OsContextSpecific::Init(PMOS_CONTEXT pOsDriverContext)
m_use64BitRelocs = true;

#ifndef ANDROID
m_intelContext = mos_gem_context_create(pOsDriverContext->bufmgr);
m_intelContext = mos_gem_context_create_v2(pOsDriverContext->bufmgr);
if (m_intelContext == nullptr)
{
MOS_OS_ASSERTMESSAGE("mos_gem_context_create_v2 failed. Fall back to mos_gem_context_create.");
m_intelContext = mos_gem_context_create(pOsDriverContext->bufmgr);
}

if (m_intelContext == nullptr)
{
Expand Down

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