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pcm-pcie.x result seems not right #68

Answered by xerothermic
cooljiansir asked this question in Q&A
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Hi @cooljiansir,

Thanks for reporting. I see two issues to be addressed in pcm-pcie program.

  1. Xeon E5 based machine (prior to Skylake), the PCIe Rd (B) column is reporting wrong number.
  2. Xeon Platinum based machine, the stats is off for both read and write.

To answer 1) Currently, PCIe Rd (B) is estimating bandwidth using sum(PCIeRdCur + CRd + DRd) * 64. CRd and DRd are generally traffics coming from CPU (sometimes service IO requests when BIOS changes PCIe Read to use CRd or DRd coherent flow). We will drop the CRd and DRd from PCIe Rd bandwidth calculation, so CPU traffic will not be estimated in the future.

To answer 2) I think there is a bug that skylake version of pcm-pcie.x is repor…

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Converted from issue

This discussion was converted from issue #68 on December 09, 2020 12:00.