ADL: Release v1.26 event files

This commit releases ADL v1.26 events and updates mapfile.csv accordingly.
intel · Apr 5, 2024 · 0052e68 · 0052e68
1 parent dcfb027
commit 0052e68
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Showing 5 changed files with 118 additions and 40 deletions.
diff --git a/ADL/events/alderlake_goldencove_core.json b/ADL/events/alderlake_goldencove_core.json
@@ -1,9 +1,9 @@
 {
   "Header": {
-    "Copyright": "Copyright (c) 2001 - 2023 Intel Corporation. All rights reserved.",
-    "Info": "Performance Monitoring Events for 12th and 13th Generation Intel(R) Core(TM) Processor - V1.24",
-    "DatePublished": "12/04/2023",
-    "Version": "1.24",
+    "Copyright": "Copyright (c) 2001 - 2024 Intel Corporation. All rights reserved.",
+    "Info": "Performance Monitoring Events for 12th and 13th Generation Intel(R) Core(TM) Processor - V1.26",
+    "DatePublished": "04/03/2024",
+    "Version": "1.26",
     "Legend": ""
   },
   "Events": [
@@ -2165,6 +2165,32 @@
       "PDISTCounter": "0",
       "Speculative": "1"
     },
+    {
+      "EventCode": "0x40",
+      "UMask": "0xF",
+      "EventName": "SW_PREFETCH_ACCESS.ANY",
+      "BriefDescription": "Counts the number of PREFETCHNTA, PREFETCHW, PREFETCHT0, PREFETCHT1 or PREFETCHT2 instructions executed.",
+      "PublicDescription": "Counts the number of PREFETCHNTA, PREFETCHW, PREFETCHT0, PREFETCHT1 or PREFETCHT2 instructions executed.",
+      "Counter": "0,1,2,3",
+      "PEBScounters": "0,1,2,3",
+      "SampleAfterValue": "100003",
+      "MSRIndex": "0x00",
+      "MSRValue": "0x00",
+      "Precise": "0",
+      "CollectPEBSRecord": "2",
+      "TakenAlone": "0",
+      "CounterMask": "0",
+      "Invert": "0",
+      "EdgeDetect": "0",
+      "PEBS": "0",
+      "Data_LA": "0",
+      "L1_Hit_Indication": "0",
+      "Errata": "null",
+      "Offcore": "0",
+      "Deprecated": "0",
+      "PDISTCounter": "0",
+      "Speculative": "1"
+    },
     {
       "EventCode": "0x43",
       "UMask": "0xfd",
@@ -2768,7 +2794,7 @@
       "UMask": "0x08",
       "EventName": "IDQ.DSB_CYCLES_OK",
       "BriefDescription": "Cycles DSB is delivering optimal number of Uops",
-      "PublicDescription": "Counts the number of cycles where optimal number of uops was delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB).",
+      "PublicDescription": "Counts the number of cycles where optimal number of uops was delivered to the Instruction Decode Queue (IDQ) from the DSB (Decode Stream Buffer) path. Count includes uops that may 'bypass' the IDQ.",
       "Counter": "0,1,2,3",
       "PEBScounters": "0,1,2,3",
       "SampleAfterValue": "2000003",
@@ -3517,6 +3543,32 @@
       "PDISTCounter": "0",
       "Speculative": "1"
     },
+    {
+      "EventCode": "0xa5",
+      "UMask": "0x01",
+      "EventName": "RS.EMPTY_RESOURCE",
+      "BriefDescription": "Cycles when Reservation Station (RS) is empty due to a resource in the back-end",
+      "PublicDescription": "Cycles when Reservation Station (RS) is empty due to a resource in the back-end",
+      "Counter": "0,1,2,3,4,5,6,7",
+      "PEBScounters": "0,1,2,3,4,5,6,7",
+      "SampleAfterValue": "1000003",
+      "MSRIndex": "0x00",
+      "MSRValue": "0x00",
+      "Precise": "0",
+      "CollectPEBSRecord": "2",
+      "TakenAlone": "0",
+      "CounterMask": "0",
+      "Invert": "0",
+      "EdgeDetect": "0",
+      "PEBS": "0",
+      "Data_LA": "0",
+      "L1_Hit_Indication": "0",
+      "Errata": "null",
+      "Offcore": "0",
+      "Deprecated": "0",
+      "PDISTCounter": "0",
+      "Speculative": "1"
+    },
     {
       "EventCode": "0xa5",
       "UMask": "0x07",
@@ -3803,6 +3855,32 @@
       "PDISTCounter": "0",
       "Speculative": "1"
     },
+    {
+      "EventCode": "0xa6",
+      "UMask": "0xC",
+      "EventName": "EXE_ACTIVITY.2_3_PORTS_UTIL",
+      "BriefDescription": "Cycles total of 2 or 3 uops are executed on all ports and Reservation Station (RS) was not empty.",
+      "PublicDescription": "Cycles total of 2 or 3 uops are executed on all ports and Reservation Station (RS) was not empty.",
+      "Counter": "0,1,2,3,4,5,6,7",
+      "PEBScounters": "0,1,2,3,4,5,6,7",
+      "SampleAfterValue": "2000003",
+      "MSRIndex": "0x00",
+      "MSRValue": "0x00",
+      "Precise": "0",
+      "CollectPEBSRecord": "2",
+      "TakenAlone": "0",
+      "CounterMask": "0",
+      "Invert": "0",
+      "EdgeDetect": "0",
+      "PEBS": "0",
+      "Data_LA": "0",
+      "L1_Hit_Indication": "0",
+      "Errata": "null",
+      "Offcore": "0",
+      "Deprecated": "0",
+      "PDISTCounter": "0",
+      "Speculative": "1"
+    },
     {
       "EventCode": "0xa8",
       "UMask": "0x01",

diff --git a/ADL/events/alderlake_gracemont_core.json b/ADL/events/alderlake_gracemont_core.json
@@ -1,9 +1,9 @@
 {
   "Header": {
-    "Copyright": "Copyright (c) 2001 - 2023 Intel Corporation. All rights reserved.",
-    "Info": "Performance Monitoring Events for 12th and 13th Generation Intel(R) Core(TM) Processor - V1.24",
-    "DatePublished": "12/04/2023",
-    "Version": "1.24",
+    "Copyright": "Copyright (c) 2001 - 2024 Intel Corporation. All rights reserved.",
+    "Info": "Performance Monitoring Events for 12th and 13th Generation Intel(R) Core(TM) Processor - V1.26",
+    "DatePublished": "04/03/2024",
+    "Version": "1.26",
     "Legend": ""
   },
   "Events": [

diff --git a/ADL/events/alderlake_uncore.json b/ADL/events/alderlake_uncore.json
@@ -1,9 +1,9 @@
 {
   "Header": {
-    "Copyright": "Copyright (c) 2001 - 2023 Intel Corporation. All rights reserved.",
-    "Info": "Performance Monitoring Events for 12th and 13th Generation Intel(R) Core(TM) Processor - V1.24",
-    "DatePublished": "12/04/2023",
-    "Version": "1.24",
+    "Copyright": "Copyright (c) 2001 - 2024 Intel Corporation. All rights reserved.",
+    "Info": "Performance Monitoring Events for 12th and 13th Generation Intel(R) Core(TM) Processor - V1.26",
+    "DatePublished": "04/03/2024",
+    "Version": "1.26",
     "Legend": ""
   },
   "Events": [

diff --git a/ADL/events/alderlake_uncore_experimental.json b/ADL/events/alderlake_uncore_experimental.json
@@ -1,9 +1,9 @@
 {
   "Header": {
-    "Copyright": "Copyright (c) 2001 - 2023 Intel Corporation. All rights reserved.",
-    "Info": "Performance Monitoring Events for 12th and 13th Generation Intel(R) Core(TM) Processor - V1.24",
-    "DatePublished": "12/04/2023",
-    "Version": "1.24",
+    "Copyright": "Copyright (c) 2001 - 2024 Intel Corporation. All rights reserved.",
+    "Info": "Performance Monitoring Events for 12th and 13th Generation Intel(R) Core(TM) Processor - V1.26",
+    "DatePublished": "04/03/2024",
+    "Version": "1.26",
     "Legend": ""
   },
   "Events": [

diff --git a/mapfile.csv b/mapfile.csv
@@ -132,29 +132,29 @@ GenuineIntel-6-6C,V1.24,/ICX/events/icelakex_uncore.json,uncore,,,
 GenuineIntel-6-6C,V1.24,/ICX/events/icelakex_uncore_experimental.json,uncore experimental,,,
 GenuineIntel-6-96,V1.05,/EHL/events/elkhartlake_core.json,core,,,
 GenuineIntel-6-9C,V1.05,/EHL/events/elkhartlake_core.json,core,,,
-GenuineIntel-6-97,V1.24,/ADL/events/alderlake_gracemont_core.json,hybridcore,0x20,0x000001,Atom
-GenuineIntel-6-97,V1.24,/ADL/events/alderlake_goldencove_core.json,hybridcore,0x40,0x000001,Core
-GenuineIntel-6-97,V1.24,/ADL/events/alderlake_uncore.json,uncore,,,
-GenuineIntel-6-97,V1.24,/ADL/events/alderlake_uncore_experimental.json,uncore experimental,,,
-GenuineIntel-6-9A,V1.24,/ADL/events/alderlake_gracemont_core.json,hybridcore,0x20,0x000001,Atom
-GenuineIntel-6-9A,V1.24,/ADL/events/alderlake_goldencove_core.json,hybridcore,0x40,0x000001,Core
-GenuineIntel-6-9A,V1.24,/ADL/events/alderlake_uncore.json,uncore,,,
-GenuineIntel-6-9A,V1.24,/ADL/events/alderlake_uncore_experimental.json,uncore experimental,,,
-GenuineIntel-6-B7,V1.24,/ADL/events/alderlake_gracemont_core.json,hybridcore,0x20,0x000001,Atom
-GenuineIntel-6-B7,V1.24,/ADL/events/alderlake_goldencove_core.json,hybridcore,0x40,0x000001,Core
-GenuineIntel-6-B7,V1.24,/ADL/events/alderlake_uncore.json,uncore,,,
-GenuineIntel-6-B7,V1.24,/ADL/events/alderlake_uncore_experimental.json,uncore experimental,,,
-GenuineIntel-6-BA,V1.24,/ADL/events/alderlake_gracemont_core.json,hybridcore,0x20,0x000001,Atom
-GenuineIntel-6-BA,V1.24,/ADL/events/alderlake_goldencove_core.json,hybridcore,0x40,0x000001,Core
-GenuineIntel-6-BA,V1.24,/ADL/events/alderlake_uncore.json,uncore,,,
-GenuineIntel-6-BA,V1.24,/ADL/events/alderlake_uncore_experimental.json,uncore experimental,,,
-GenuineIntel-6-BF,V1.24,/ADL/events/alderlake_gracemont_core.json,hybridcore,0x20,0x000001,Atom
-GenuineIntel-6-BF,V1.24,/ADL/events/alderlake_goldencove_core.json,hybridcore,0x40,0x000001,Core
-GenuineIntel-6-BF,V1.24,/ADL/events/alderlake_uncore.json,uncore,,,
-GenuineIntel-6-BF,V1.24,/ADL/events/alderlake_uncore_experimental.json,uncore experimental,,,
-GenuineIntel-6-BE,V1.24,/ADL/events/alderlake_gracemont_core.json,core,,,
-GenuineIntel-6-BE,V1.24,/ADL/events/alderlake_uncore.json,uncore,,,
-GenuineIntel-6-BE,V1.24,/ADL/events/alderlake_uncore_experimental.json,uncore experimental,,,
+GenuineIntel-6-97,V1.26,/ADL/events/alderlake_gracemont_core.json,hybridcore,0x20,0x000001,Atom
+GenuineIntel-6-97,V1.26,/ADL/events/alderlake_goldencove_core.json,hybridcore,0x40,0x000001,Core
+GenuineIntel-6-97,V1.26,/ADL/events/alderlake_uncore.json,uncore,,,
+GenuineIntel-6-97,V1.26,/ADL/events/alderlake_uncore_experimental.json,uncore experimental,,,
+GenuineIntel-6-9A,V1.26,/ADL/events/alderlake_gracemont_core.json,hybridcore,0x20,0x000001,Atom
+GenuineIntel-6-9A,V1.26,/ADL/events/alderlake_goldencove_core.json,hybridcore,0x40,0x000001,Core
+GenuineIntel-6-9A,V1.26,/ADL/events/alderlake_uncore.json,uncore,,,
+GenuineIntel-6-9A,V1.26,/ADL/events/alderlake_uncore_experimental.json,uncore experimental,,,
+GenuineIntel-6-B7,V1.26,/ADL/events/alderlake_gracemont_core.json,hybridcore,0x20,0x000001,Atom
+GenuineIntel-6-B7,V1.26,/ADL/events/alderlake_goldencove_core.json,hybridcore,0x40,0x000001,Core
+GenuineIntel-6-B7,V1.26,/ADL/events/alderlake_uncore.json,uncore,,,
+GenuineIntel-6-B7,V1.26,/ADL/events/alderlake_uncore_experimental.json,uncore experimental,,,
+GenuineIntel-6-BA,V1.26,/ADL/events/alderlake_gracemont_core.json,hybridcore,0x20,0x000001,Atom
+GenuineIntel-6-BA,V1.26,/ADL/events/alderlake_goldencove_core.json,hybridcore,0x40,0x000001,Core
+GenuineIntel-6-BA,V1.26,/ADL/events/alderlake_uncore.json,uncore,,,
+GenuineIntel-6-BA,V1.26,/ADL/events/alderlake_uncore_experimental.json,uncore experimental,,,
+GenuineIntel-6-BF,V1.26,/ADL/events/alderlake_gracemont_core.json,hybridcore,0x20,0x000001,Atom
+GenuineIntel-6-BF,V1.26,/ADL/events/alderlake_goldencove_core.json,hybridcore,0x40,0x000001,Core
+GenuineIntel-6-BF,V1.26,/ADL/events/alderlake_uncore.json,uncore,,,
+GenuineIntel-6-BF,V1.26,/ADL/events/alderlake_uncore_experimental.json,uncore experimental,,,
+GenuineIntel-6-BE,V1.26,/ADL/events/alderlake_gracemont_core.json,core,,,
+GenuineIntel-6-BE,V1.26,/ADL/events/alderlake_uncore.json,uncore,,,
+GenuineIntel-6-BE,V1.26,/ADL/events/alderlake_uncore_experimental.json,uncore experimental,,,
 GenuineIntel-6-AA,V1.08,/MTL/events/meteorlake_crestmont_core.json,hybridcore,0x20,0x000002,Atom
 GenuineIntel-6-AA,V1.08,/MTL/events/meteorlake_redwoodcove_core.json,hybridcore,0x40,0x000002,Core
 GenuineIntel-6-AA,V1.08,/MTL/events/meteorlake_uncore.json,uncore,,,