ICX: Release v1.24 event files

This commit releases ICX v1.24 events and updates mapfile.csv accordingly.
intel · Mar 14, 2024 · d883888 · d883888
1 parent 21a8be3
commit d883888
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Showing 4 changed files with 92 additions and 74 deletions.
diff --git a/ICX/events/icelakex_core.json b/ICX/events/icelakex_core.json
@@ -1,9 +1,9 @@
 {
   "Header": {
-    "Copyright": "Copyright (c) 2001 - 2023 Intel Corporation. All rights reserved.",
-    "Info": "Performance Monitoring Events for 3rd Generation Intel(R) Xeon(R) Processor Scalable Family based on Ice Lake microarchitecture - V1.23",
-    "DatePublished": "11/14/2023",
-    "Version": "1.23",
+    "Copyright": "Copyright (c) 2001 - 2024 Intel Corporation. All rights reserved.",
+    "Info": "Performance Monitoring Events for 3rd Generation Intel(R) Xeon(R) Processor Scalable Family based on Ice Lake microarchitecture - V1.24",
+    "DatePublished": "03/12/2024",
+    "Version": "1.24",
     "Legend": ""
   },
   "Events": [
@@ -2052,7 +2052,7 @@
       "UMask": "0x08",
       "EventName": "IDQ.DSB_CYCLES_OK",
       "BriefDescription": "Cycles DSB is delivering optimal number of Uops",
-      "PublicDescription": "Counts the number of cycles where optimal number of uops was delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB).",
+      "PublicDescription": "Counts the number of cycles where optimal number of uops was delivered to the Instruction Decode Queue (IDQ) from the DSB (Decode Stream Buffer) path. Count includes uops that may 'bypass' the IDQ.",
       "Counter": "0,1,2,3",
       "PEBScounters": "0,1,2,3",
       "SampleAfterValue": "2000003",
@@ -5111,7 +5111,7 @@
       "CounterMask": "0",
       "Invert": "0",
       "EdgeDetect": "0",
-      "PEBS": "0",
+      "PEBS": "1",
       "Data_LA": "0",
       "L1_Hit_Indication": "0",
       "Errata": "null",

diff --git a/ICX/events/icelakex_uncore.json b/ICX/events/icelakex_uncore.json
@@ -1,9 +1,9 @@
 {
   "Header": {
-    "Copyright": "Copyright (c) 2001 - 2023 Intel Corporation. All rights reserved.",
-    "Info": "Performance Monitoring Events for 3rd Generation Intel(R) Xeon(R) Processor Scalable Family based on Ice Lake microarchitecture - V1.23",
-    "DatePublished": "11/14/2023",
-    "Version": "1.23",
+    "Copyright": "Copyright (c) 2001 - 2024 Intel Corporation. All rights reserved.",
+    "Info": "Performance Monitoring Events for 3rd Generation Intel(R) Xeon(R) Processor Scalable Family based on Ice Lake microarchitecture - V1.24",
+    "DatePublished": "03/12/2024",
+    "Version": "1.24",
     "Legend": ""
   },
   "Events": [
@@ -4812,6 +4812,42 @@
       "Deprecated": "0",
       "FILTER_VALUE": "0",
       "CounterType": "PGMABLE"
+    },
+    {
+      "Unit": "CHA",
+      "EventCode": "0x35",
+      "UMask": "0x04",
+      "PortMask": "0x00",
+      "FCMask": "0x00",
+      "UMaskExt": "0xC8F37F",
+      "EventName": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR_REMOTE",
+      "BriefDescription": "PCIRDCUR (read) transactions from an IO device that addresses memory on a remote socket",
+      "PublicDescription": "TOR Inserts : PCIRdCurs issued by IO Devices and targets remote memory : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+      "Counter": "0,1,2,3",
+      "ELLC": "0",
+      "Filter": "na",
+      "ExtSel": "0",
+      "Deprecated": "0",
+      "FILTER_VALUE": "0",
+      "CounterType": "PGMABLE"
+    },
+    {
+      "Unit": "CHA",
+      "EventCode": "0x35",
+      "UMask": "0x04",
+      "PortMask": "0x00",
+      "FCMask": "0x00",
+      "UMaskExt": "0xC8F2FF",
+      "EventName": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR_LOCAL",
+      "BriefDescription": "PCIRDCUR (read) transactions from an IO device that addresses memory on the local socket",
+      "PublicDescription": "TOR Inserts : PCIRdCurs issued by IO Devices and targets local memory : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+      "Counter": "0,1,2,3",
+      "ELLC": "0",
+      "Filter": "na",
+      "ExtSel": "0",
+      "Deprecated": "0",
+      "FILTER_VALUE": "0",
+      "CounterType": "PGMABLE"
     }
   ]
 }